This document discusses serial communication using the 8085 microprocessor and 8251A USART chip. It describes the basics of synchronous and asynchronous serial transmission including start/stop bits and framing. It provides details on the RS-232 serial interface standard including voltage levels, connectors, and DTE/DCE roles. The 8251A USART chip is explained in detail, including its block diagram, pinout, registers for control, status, and data, and how it converts parallel to serial and vice versa. Modes of operation and initialization of the 8251A are also covered.

1. SERIAL I/O WITH 8085

2. Basics of serial communication

3. SERIAL I/0 MODE DEVICE MODEM (SERIAL) PROCESSOR (PARALLEL) PARALLEL TO SERIAL SERIAL TO PARALLEL

5. SYNCHRONOUS TRANSMISSION CLK TRANSMITTER RECEIVER SYNC SYNC DATA

6. ASYNCHRONOUS TRANSMISSIONStart and stop bits

9. WHEN NO DATA IS TRANSMITTED RECEIVER STAYS AT LOGIC 1 CALLED MARK ; LOGIC 0 CALLED SPACE

11. TTL to RS-232

14. VOLTAGE LEVEL +3V TO +15 V LOGIC 0 VOLTAGE LEVEL -3V TO -15 V LOGIC 1 YEP…. THATS RIGHT….. HERE WE USE NEGATIVE TRUE LOGIC BUT USUSALLY LOGIC 1  +12V LOGIC 0-12V ????!!!!!!

17. SIGNALS OF RS232

18. We are concerned about,

23. Bit rate (bits/sec): actual rate at which bits are transmitted

25. DTE Vs DTE DTE DTE TX TX 2 2 RX RX 3 3 GND 7 7 *NULL MODEM CONNECTION

26. Typical System Connections 7 7

28. DATA TX MPU converts parallel to serial

29. DATA RX  MPU converts serial to parallel

30. Synchronization between MPU and slow peripheralUSART – Universal Synchronous /Asynchronous Receiver/ Transmitter It incorporates all the above features in a single chip and other sophisticated functions for serial communication. It is a programmable device i.e its functions and specifications for serial i/o can be determined by writing instructions to its internal registers 8251A USART  device widely used for serial i/o

31. The 8251A Programmable Communication Interface 8251A

32. 8251A- BLOCK DIAGRAM

34. 8251A- PIN DIAGRAM

37. CONTROL REG

39. LOGIC 0 8251 is selected by the MPU

40. RD’ – READ SIGNAL

41. LOGIC 0  The MPU reads the status from status register or accepts input from data buffer

42. WR’ – WRITE SIGNAL

44. LOGIC 0 data buffer is addressed

45. LOGIC 1  control register or status register is addressed

47. LOGIC 1  forces 8251 to RESET and enters into idle mode

48. CLK - clock

49. REFERS TO SYSTEM CLOCK

52. 16 BIT REGISTER

53. first byte  MODE INSTRUCTION ( WORD )

54. second byte  COMMAND INSTRUCTION ( WORD )

55. Register can be accessed when C/D’ is HIGH and WR’ is LOW

56. STATUS REGISTER

57. Input register that checks the READY status of the peripheral

58. Register can be accessed when C/D’ is HIGH and RD’ is LOW

59. DATA REGISTER

60. 8 BIT bidirectional register – addressed as input or output

62. OUTPUT SIGNAL : TXD - TRANSMIT DATA SERIAL BITS ARE TRANSMITTED ON THIS LINE TxRDY – TRANSMITTER READY LOGIC 1 – BUFFER EMPTY; USART READY TO ACCEPT TO INTERRUPT MPU or INDICATE STATUS TxE – TRANSMITTER EMPTY LOGIC 1 – OUTPUT REGISTER IS EMPTY LOGIC 0 - BYTE IS TRANSFERRED FROM BUFFER TO REG.

63. RECEIVER SECTION RECEIVER - CONVERTS SERIAL TO PARALLEL TWO REGISTERS - INPUT REGISTER – TO HOLD SERIAL 8 BITS WITH START & STOP BITS AND CONVERT THEM TO PARALLEL - BUFFER REGISTER – TO STORE PARALLEL BITS TWO INPUT AND ONE OUTPUT SIGNALS INPUT SIGNAL : RXC’ - RECEIVER CLOCK CONTROLS THE RATE AT WHICH BITS ARE RECEIVED BY USART CLOCK FREQ – 1/16/64 TIMES THE BAUD

64. RXD - RECEIVE DATA SERIAL BITS ARE RECEIVED ON THIS LINE OUTPUT SIGNAL : RxRDY – RECEIVER READY LOGIC 1 – USART HAS A CHARACTER IN THE BUFFER REGISTER NAD READY TO TRANSFER TO MPU TO INTERRUPT MPU or INDICATE STATUS

65. 7 6 5 4 3 2 1 0 Mode register Number of Stop bits Baud Rate 00: Syn. Mode 01: ASYNC x1 10: ASYNC x16 11: ASYNC x64 00: invalid 01: 1 bit 10: 1.5 bits 11: 2 bits Character length 00: 5 bits 01: 6 bits 10: 7 bits 11: 8 bits 8251 mode register- MODE WORD PARITY CONTROL X0 – NO PARITY 01 – ODD PARITY 11 – EVEN PARITY

66. Command Register

67. Status Register

68. INITIALISING THE 8251A MPU INFORMS 8251 – MODE, BAUD, STOP BITS, PARITY CONTROL WORDS TO BE LOADED FROM MPU TO 8251

69. OPERATION FLOW