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11 Serial 0515
11 Serial 0515
11 Serial 0515
11 Serial 0515
11 Serial 0515
11 Serial 0515
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11 Serial 0515

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  • 1. Section 17.1 Objectives Upon completion of this chapter, you will be able to: List the advantages of serial communication over parallel communication CMPE328 Microprocessors Explain the difference between synchronous and (Spring 2007-08) asynchronous communication Define the terms simplex, half duplex, and full duplex and diagram their implementation in serial communication Serial Interfacing Describe how start and stop bits frame data for serial communication Compare the measures baud rate and bps (bits per second) By Dr. Mehmet Bodur Describe the RS232 standard Compare DTE (data terminal) versus DCE (data communication) equipment Describe the purpose of handshaking signals such as DTR, RTS, and CTS Describe the operation of a USART and use and 8251 IC CMPE328 Spring 2007-08 Dr.Mehmet Bodur, EMU-CMPE 2 Section 17.1 Section 17.1 Basics of Serial Communication Simplex vs Duplex Microprocessors are based mostly on 8-bit In Simplex Mode data flow Transmitter Receiver is in one direction only. registers. Thus, their fastest I/O is 8-bit In Half Duplex Mode data parallel ports. flows in one direction, at a Transmitter 0 1 Transmitter given time, Receiver Receiver 1 0 But, wiring cost of a long distance A protocol and switches connect the devices both to communication is very expensive if you receive and also to transmit. carry 8-wires. In Full Duplex mode, transmitted data and Remedy is to transfer data serially in bits received data goes Transmitter Transmitter instead of in bytes or words. simultaneously through two Receiver Receiver channels. CMPE328 Spring 2007-08 Dr.Mehmet Bodur, EMU-CMPE 3 CMPE328 Spring 2007-08 Dr.Mehmet Bodur, EMU-CMPE 4
  • 2. Section 17.1 Section 17.1 Asynchronous Transmission Asynchronous vs Synchronous How can the receiver get each data bit when it is Start and Stop Bits delivered by the transmitter? Start bit is required to synchronize the internal In synchronous transmission an explicit clock clock of receiver. signal describes the instants of valid data. Stop bit is required to test the clock frequency. A single data bit is sent at each clock. Only DATA is transmitted, internal clock is generated locally. Voltage levels are 0 and 5V (TTL signal) Minimum three signal lines required for full duplex, Receive-DATA, Transmit-DATA, and CLOCK. TTL DATA In asynchronous transmission clock is derived internal using a-priory parameters and a start bit. clock Start D0 D1 D2 D3 D4 D5 D6 D7 Stop Transfer rate known, internal clock starts to pulse with 0 1 0 1 0 0 1 1 0 1 the start bit, at the known transfer rate. Internal clock stops with the time Internal clock starts Bits are sampled at Ony two signal lines required for full duplex the rising edge of stop bit. If Stop bit is not with the start bit. high, it gives framing error. Receive-DATA and Transmit-DATA the internal clock bit#: 7 6 5 4 3 2 1 0 Data is 01100101b =65h. It is ASCII “e” CMPE328 Spring 2007-08 Dr.Mehmet Bodur, EMU-CMPE 5 CMPE328 Spring 2007-08 Dr.Mehmet Bodur, EMU-CMPE 6 Section 17.1 Section 17.1 Computers may be Asynchronous connected to eachother at COM port or TTL signal Communication System Data Transfer Rate levels as well. 1488 and 1489 COM port CPU BUS MODEM Transmit DRIVER Transmit Both devices shall know the data transfer System UART Phone Line Bus rate of the communication to synchronize Receive Receive the internal clocks correctly. TTL Level Signals RS232 Level Signals Data transfer rate is measured in BAUD Baud = bit/second Phone BUS Telecommunication Media MODEM DRIVER CPU (including start, stop, data, parity etc.) Transmit UART Transmit System Bus kilo Baud = 1000 Baud. (not 1024 Baud) Receive Receive Mega Baud = 1000 000 Baud RS232 TTL Level Level Signals Signals CMPE328 Spring 2007-08 Dr.Mehmet Bodur, EMU-CMPE 7 CMPE328 Spring 2007-08 Dr.Mehmet Bodur, EMU-CMPE 8
  • 3. Section 17.1 Baud Rate Calculations Packet transmission time If each bit takes T seconds, the baud rate is B= 1/T. If a system sends a packet of 50 bytes at Standard Baudrates are 150, 300, 600, 1200, 2400, 4800, 9600, 19200, etc. 1200 Baud, using 8-data, no-parity, one Baudrate tolerance for a10-bit frame is 5%. stop bits, what is the transmission time of Example: T=209μs B= 1/T = 4785 Baud the whole packet: it is 4800 Baud within 5% tolerance. 1-byte frame is 1-start + 8-data + 1-stop bit one frame period = 10 bits/byte. T packet is transferred by 50 x 10 bits = 500 bits on the serial communication line. Tpacket = 500 bits / 1200 Baud = 0.417sec. Start D0 D1 D2 D3 D4 D5 D6 D7 Stop = 417 milliseconds. 0 1 0 1 0 0 1 1 0 1 time bits 7 6 5 4 3 2 1 0 the transmitted data value is 01100101 b = 65h =‘e’ CMPE328 Spring 2007-08 Dr.Mehmet Bodur, EMU-CMPE 9 CMPE328 Spring 2007-08 Dr.Mehmet Bodur, EMU-CMPE 10 Section 17.1 Section 17.1 RS232 Socket Pins Handshaking Signals Recommended standard describe two kind of sockets. DTE DCE Modem-Terminal handshaking signals: TxD 2 TxD 2 DTE: Device Terminal Equipment. RxD 3 RxD 3 Device status signals Computers, Terminals, etc. GND 7 GND 7 DTR: Data terminal ready (DTE is ok.). DCE: Device Communication Equipment DSR: Data Set ready (DCE is ok.) Modem (modulator-demodulator). Equipment connections: Flow control signals DTE DTE RTS: Request to Send (DTE sends char.) DTE is connected to DCE TxD 2 TxD 2 without crossing. RxD 3 RxD 3 CTS: Clear to Send (DCE accepts RTS) DTE is connected to DTE GND 7 GND 7 cross-wired. CMPE328 Spring 2007-08 Dr.Mehmet Bodur, EMU-CMPE 11 CMPE328 Spring 2007-08 Dr.Mehmet Bodur, EMU-CMPE 12
  • 4. Section 17.4 Section 17.4 UART 8251 8251 UART Device Register addressing 8251 USART A processor may transmit/receive data in ~CS C/~D=00 (data) TXRDY serial format without any extra hardware. writes to the transmit buffer D[0..7] TXE ~TXC But it costs to the processing time of the reads from the receive buffer TXD RXD processor. ~CS C/~D=01 (control) RESET RXRDY A UART (Universal Asynchronous Receiver Transmitter) is writes to the CLK ~RXC SY/BR a hardware device that shifts out data bits mode register right after a reset. C/~D DSR to transmit a data byte, and also shifts-in command register after mode is ~RD ~DTR ~WR ~CTS data bits to receive a data byte. written. ~CS ~RTS reads from the status register. CMPE328 Spring 2007-08 Dr.Mehmet Bodur, EMU-CMPE 13 CMPE328 Spring 2007-08 Dr.Mehmet Bodur, EMU-CMPE 14 Section 17.4 Section 17.4 8251 system bus connection 8251 Clock Signals 8251 USART CLK is system clock input TXRDY 8251 USART Data buffer D[0..7] D[0..7] TXE Transmit TXC and RXC are transmit-receive TXRDY Clock address is 308h ~TXC TXD serial clock inputs. D[0..7] TXE ~TXC data There are three baudrate factors Control/Status RXD TXD RXD RXRDY Receive divide by 1, 16 and 64. address is 309h, RESET RESET ~RXC Clock Example. Find RXC oscillator frequency RXRDY CLK CLK RESET ~RXC TXRDY and A0 C/~D SY/BR Clock Generator for 1200 Baud operation with baudrate CLK SY/BR DSR factor 1/64. C/~D RXRDY are for ~IOR ~RD ~DTR modem DSR ~IOW ~WR Solution: fRXC =1200*64 Hz = 76.8 kHz. ~RD interrupted Address ~CS ~CTS ~RTS handshaking Example: What shall be the baudrate ~WR ~DTR ~CTS Decoder ~308h – ~309h operation. factor for 4800 Baud operation if RXC is ~CS ~RTS connected to 19.2 kHz ? Solution: 19.2kHz/4.8kHz = 4, 1/4 CMPE328 Spring 2007-08 Dr.Mehmet Bodur, EMU-CMPE 15 CMPE328 Spring 2007-08 Dr.Mehmet Bodur, EMU-CMPE 16
  • 5. Section 17.4 Section 17.4 8251 mode/control settings 8251 Reset Sequence 8251 USART Mode Register format for asynchronous mode: and status bits b7 b6 = { S2S1: nr.of stop bits 00: invalid / 01:1stop / 10: 1.5stop / 11: 2stop }, 8251 reset sequence is b5 b4 = { EP: parity type 0: odd / 1: even }, = { PEN: parity enable 0: no-parity-bits / 1: parity-bits-present }, write three successive zeros to control address to b3 b2 = { L2L1: nr.of data bits 00: 5-bit / 01: 6-bit / 10: 7-bit / 11: 8-bit }, b1 b0 = { B2B1: baud rate factor 00: sync-mode / 01: /1 / 10: /16 / 11: /64 } assure writing a reset to the command register. Control Register format for asynchronous mode: b7 = { EH: Enter hunt mode to search sync char 1: enable / 0: disable } write command 40h to reset (reset chip) b6 = { IR: Internal reset 1: resets the 8251A } b5 = { RTS: Request to send, 1: RTS-output-forced-to-low } After the reset, 8251 expects mode settings. b4 = { ER: Error Reset 1: reset error flags PE,OE,FE } b3 = { SBRK: Send break char 1: forces TxD low } write the mode settings to control address b2 = { RxE: Receiver enable 1: enable, 0: disable } b1 = { DTR: Data terminal ready 1: DTR-output-forced-to-low } There after 8251 needs command settings. b0 = { TxE: Transmitter enable 1: enable, 0: disable } Status Register format for asynchronous mode: write command for command settings. b7 = {DSR 1: DSR pin is active (low)} b6 = {SY/BD 1: sync-or-break char detected} Now the device is ready for transmit and receive b5 = {FE 1: Framing error occurs} b4 = {OE 1: Overrun error occurs} operations b3 = {PE 1: Parity error occurs} b2 = {TxE 1: Tx finished transmitting all data} b1 = {RxRDY 1: Data-in buffer is full} b0 = {TxRDY 1: Data-out buffer is empty} CMPE328 Spring 2007-08 Dr.Mehmet Bodur, EMU-CMPE 17 CMPE328 Spring 2007-08 Dr.Mehmet Bodur, EMU-CMPE 18 Section 17.4 For the circuit 8251 initialization For the circuit with ports 8251 coding with ports 308h, 308h, 309h enabling 309h enabling Mode Register 8251, write a code mainloop b7 b6 = { S2S1: nr.of stop bits 00: inval./ 01:1stop / 10: 1.5stop / 11: 2stop }, .model small 8251, write a b5 = { EP: parity type 0: odd / 1: even }, a) to initialize it for 1200 .code …. code b4 = { PEN: parity enable 0: no-parity-bits / 1: parity-bits-present }, baud when TXC ; reset 8251 ; read the port a) to initialize it for b3 b2 ={ L2L1: nr.of data bits 00: 5-bit / 01: 6-bit / 10: 7-bit / 11: 8-bit }, connected to 19.2kHz, to mov dx,309h mov dx,300h 1200 baud when b1 b0 ={ B2B1: baud rate factor 00: sync-mode / 01: 1 / 10: 16 / 11: 64 } transmit characters to a mov al,0 in al,dx TXC connected to Control Register DCE with 8-bit data, no mov ah,al ; save it 19.2kHz, to b7 = { EH: Enter hunt mode to search sync char 1: enable / 0: disable } parity, one stop bit out dx,al transmit b6 = { IR: Internal reset 1: resets the 8251A } configuration. out dx,al ; send the char, characters to a b5 = { RTS: Request to send, 1: RTS-output-forced-to-low } b) to read port 300h, and out dx,al ; wait if buffer is full DCE with 8-bit b4 = { ER: Error Reset 1: reset error flags PE,OE,FE } transmit the value in mov al,40h mov dh,309h data, no parity, b3 = { SBRK: Send break char 1: forces TxD low } serial format out dx,al wdataout one stop bit b2 = { RxE: Receiver enable 1: enable, 0: disable } in al,dx ; status byte b1 = { DTR: Data terminal ready 1: DTR-output-forced-to-low } ; set mode configuration. b0 = { TxE: Transmitter enable 1: enable, 0: disable } Status Register format for asynchronous mode: mov al, 4Eh and al,01h b) to read port b7 = {DSR 1: DSR pin is active (low)} jz wdataout 300h, and Mode register shall be 01001110b = 4Eh b6 = {SY/BD 1: sync-or-break char detected} out dx,al b5 = {FE 1: Framing error occurs} ; set command ; now send character transmit the value Control register shall be 00110011b = 33h b4 = {OE 1: Overrun error occurs} mov al,ah in serial format mov al, 33h b3 = {PE 1: Parity error occurs} mov dx,308h handshaking b2 = {TxE 1: Tx finished transmitting all data} out dx,al out dx,al to modem is receiver is disabled. b1 = {RxRDY 1: Data-in buffer is full} enabled. b0 = {TxRDY 1: Data-out buffer is empty} ; continue looping only transmitter enabled. jmp mainloop end CMPE328 Spring 2007-08 Dr.Mehmet Bodur, EMU-CMPE 19 CMPE328 Spring 2007-08 Dr.Mehmet Bodur, EMU-CMPE 20
  • 6. Exercise Solve the following two Final Exam questions. Final Fall 06 Final Fall 07 CMPE328 Spring 2007-08 Dr.Mehmet Bodur, EMU-CMPE 21

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