ESD: Do you need some shock therapy?!
Written by Adrian O’Shaughnessy, Senior Layout Engineer
In the electronics industry, losses associated with ESD are estimated at between a
half billion and five billion dollars annually.
An ESD damaged chip can be worse than a complete failure of a chip as a damaged chip
still may test good but cause intermittent problems or erratic behavior further down the
line. So ESD can not only destroy a component but ESD can shorten a component's life.
Having ESD awareness and following through with good ESD layout practices are
essential in reducing quality failures due to ESD. It is very important when designing and
implementing an ESD layout program to know the ESD susceptibility of the ESD sensitive
(ESDS) devices you are trying to protect. Classification of these devices should include all
simulation models such as the Human Body Model (HBM), Machine Mode (MM), Charged-
device Model (CDM) and Transmission Line Pulsing (TLP).
Figure 1 tracks ESD-related failures, as determined in Failure Mode Analysis, with
deviations from good ESD layout practices:
% of Failures
Due to ESD
Figure 1: Correlation of ESD failure occurrence and deviations from good ESD layout practices
The principles behind different ESD protection schemes must be fully understood as well
as various ESD schemes that aim to create low impedance discharge paths to shunt ESD
transients, clamp the pad voltages to sufficiently low levels and techniques that limit ESD
currents from reaching the core.
IC Mask Design’s new ESD course aims to fully explain these protection schemes as well
as various other ESD topics such as ESD device compositions, parasitic effects of ESD
structures, noise isolation, ground/power strategies, ESD electromigration issues, etc.
Let’s take a look some specific ESD layout guidelines (taken from new ICMD ESD training
Vias must be placed correctly
Electromigration is the process of conductor heating and fusing due to excessive current
and is growing as a design problem due to increased interconnect current densities related
to IC down-scaling. Care is always given to supply rails, but electromigration is very
prevalent in signal interconnect, especially ESD signal interconnect.
Contact holes and vias are particularly susceptible to electromigration. The current here
commonly encounters a narrowing of the conductive pathway and so multiple vias must
be organized such that the resulting current flow is distributed as evenly as possible
through all the vias.
Avoid 90-degree corner bends
Pay attention to bends in interconnect. 90-degree corner bends must Distribution
Figure 2: The lower left via is overloaded while the upper right via hardly carries any current at all
Avoid 90-degree corner bends
Pay attention to bends in interconnect. 90-degree corner bends must be avoided in ESD
layout structures as corners are highly stressed during ESD event. The use of 45-degree
layout is useful in certain areas and is often used for optimal routing of wide signals. It’s
also highly recommended in I/O cells in order to reduce power surge in corners and
possible spikes that can result from an ESD event.
Metal routing is critical
Avoid metal routing that results in current crowding through a device. Figure 3 shows
good and bad layout practices for metal routing. In the bottom diagram of figure 3, the
right-most finger has least metal resistance and will experience the current crowding
effect on the right side of the device.
The upper diagram shows a good layout practice for metal routing as all fingers have
equal metal resistance which ensures a more even current distribution.
Figure 3: Good and bad layout practice for metal routing
Figure 4 shows possible methods for good metal routing:
Current Current Current
Figure 4: The two figures at the right both illustrate uniform current distribution through the MOS
device. The left figure illustrates the better option for contact-to-via placement