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Dsp Datapath
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Dsp Datapath

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This project is based on Data Path Architecture which consists of Shift register, MAC Unit, 16-Bit ALU and Tri-State Buffer. This whole architecture is implemented by using VHDL and simulated by using ...

This project is based on Data Path Architecture which consists of Shift register, MAC Unit, 16-Bit ALU and Tri-State Buffer. This whole architecture is implemented by using VHDL and simulated by using Modelsim.

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    Dsp Datapath Dsp Datapath Presentation Transcript

    • AMini Project SeminaronDSP DATAPATH
      M.Tech Microelectronics
      Manipal Institute of Technology
      By:
      Abhishek Tiwari
      B. Dhaval Kumar
      K .Sravan Kumar
      Rajkumar Patidar
    • Introduction
      Datapath
      Architecture of Datapath
      Datapath in DSP Processors
      Modules using in Datapath
      Modules Function
    • Problem Definition
      DSPs
      • Performs all key arithmetic operations in 1 cycle.
      • Hardware support for managing numeric fidelity:
      • Shifters
      • Guard bits
      • Saturation
      GPPs
      • Multiplies often take >1 cycle
      • Shifts often take >1 cycle
      • Other operations typically take multiple cycles
    • DataPath:
      A datapath is a collection of functional units, registers, buffers.
      Most central processing units consist of a datapath and a control unit.
      Processor has Two Main Units in its Architecture
    • General Processor
    • Datapath
      Second Main Part in Microprocessor.
      Contains Several Unit.
      It Referred RTL Design.
    • Basic Architecture
    • A Simple DSP Processor
    • DSP Datapath
    • Modules
      Registers
      MAC
      ALU
      Shifter
      Tristate Buffer
      Control Unit
    • Registers
      Storing Multiple Bits
      Register File
      Synchronized by same Clock
      8 Bit Register, 16 Bit Register
    • Basic Register Circuit
    • Register File
    • 4 x 8 Register File
    • Design Summary
      • Word Length: 8 bit, 16 bit
      • Input Registers 8 Bit
      • Modeling : Behavioral Modeling
      • Used Generic Statement, If – Else Statement
      • ACC Reg. is 16 bit.
      • A load control Signal for enabling Storing function.
      • A Clear for reset the stored value.
      • Functions on Falling Edge.
    • Register’s Result
    • Multiply-Accumulate (MAC)
      What is MAC ?
      Multiplication followed by accumulation.
      Where is MAC Use ?
      Common operation in many digital systems, particularly those highly interconnected, like digital filters, neural networks, data quantizers, etc.
      What are the Features of MAC ?
      Multiplying two values ,then adding the result to the previously accumulated value, which must then be re-stored in the registers for future accumulations and Checking for Overflow.
    • Basic MAC Unit
      Types of Multiplier:
      1.Unsigned Multiplier
      2. Signed Multiplier
    • Design Summary
      MAC is 8-bit  A,B: 8 bit I/P Registers
      prod: 16 bit O/P Register
      2 Control Signals :- Start and Stop
      Overflow Function, which might happen when the number of MAC operations is large.
      Signed Adder
    • Timing Diagram & Result
    • Arithmetic Logic Unit
      It consists of arithmetic and logic unit.
      Arithmetic Operation : Addition Subtraction
      Logical Operation : And,or,not etc..
      It performs the operations according to control signal given
      It is basic building block of microprocessor.
    • ALU Architecture
    • Practical Modal
    • Design Summary
      ALU is 16-bit  A,B: 16 bit i/p reg
      y: 16 bit o/p register
      Control Signal is of 4-bitIt can support up to 16 different operations.
      There is a separate flag register for carry and borrow, parity and sign flag.
      Comparator is also included in this Alu design.
      ALU is working on falling edge clock.
    • Design Details:
      Addition
      variable q : std_logic_vector(16 downto 0);
      when "0000" => q := ('0'& a) + ('0'& b);
      y <= q(15 downto 0);
      if ( q(16) = '1' ) then f(3) <= '1'; --carry flag
      end if;
      f(1) <= '0'; --Sign flag is zero
      Cont………
    • Cont….
      Subtraction
      variable q : std_logic_vector(16 downto 0);
      when "0001" => q := ('0'& a) - ('0'& b);
      y <= q(15 downto 0);
      if ( q(16) = '1' ) then f(1) <= '1'; --sign flag
      end if;
      f(3) <= '0'; --Carry flag is zero
    • Cont…
      Parity and Zero flag
      variable p,z : std_logic;
      We are checking results separately for parity and zero flag for all the operations.
      Parity flag (even):
      p := y(15) xor y(14)……..…xor y(0);
      if ( p = '0') then f(2) <= '1';
      Zero flag:
      z := y(15) or y(14)……..…or y(0);
      if (z = '0') then f(0) <= '1';
    • Cont…
      Comparator
      when "1110" =>
      if(a>b)then y<="0000000000000100";
      elsif(a<b)then y<="0000000000000010";
      elsif(a=b)then y<="0000000000000001";
      f(3) <= '0';
      f(1) <= '0';
      Here instead of extra resistor for comparator o/p, o/p resistery is used for comp o/pt to save one resister.
      At later stage we can use this results by using first 3 bit of o/p resister.
    • Cont…
      Other function
      when “case" => y <= a “function” b;
      f(3) <= '0';
      f(1) <= '0';
      Syntax for functions other then addition, subtraction and comparator is like above.
      For these functions sign flag and zero flag is always zero.
    • Control Word for Different Functions
      • 1000 XNOR
      • 1001 PassA
      • 1010 Pass B
      • 1011 NOT B
      • 1100 Increment A
      • 1101 Decrement B
      • 1110 Compare A & B
      • 1111 Reset o/p
      0000 Addition
      0001 Subtraction
      0010 AND
      0011 OR
      0100 NAND
      0101 NOR
      0110 NOT A
      0111 XOR
    • ALU Results
      Addition
      • Comparator
    • Cont…
      Pass A
      A XOR B
    • Shifter
      The shifter is used for shifting bits one position either to the left or to the right.
      The Shifter operations are referred to either as shifting or rotating depends on how the end bits are shifted in or out.
      Here Shown Simple Shifter :
    • Basic Shifter Circuit
    • Design Summary
      Word Length: 16 bit
      Modeling : Behavioral Modeling
      Used case statements and if else statements.
      A ‘shift_sel’ 2-bit control Signal for selecting type of shift.
      Functions on Falling Edge.
      Operations: 00 – No Operation
      01 – Left shift by 8 bit
      10 – Right shift by 8 bit
      11 – Rotate Right by 8 bit
    • Shifter Result:
    • Tristate Buffer
      A Tristate Buffer, as the name suggest, has three states: 0, 1 & Z.
      Z : Represents High Impedance State
    • Control Unit
    • What is Control Unit
      The Control Unit inside the Processor is a FSM.
      By Stepping through a Sequence of States, it controls the operation of Datapath.
      Contains Next – State circuit, State Memory Register & Output Logic circuit.
      Control Inputs, Status Signals.
      Control output, Control Signal or Control Word.
    • Counting 1 to 10
    • Control unit Circuit
    • Control Signals
      For Registers: Load and Clear Signals
      1 bit Start signal for enable & disable the operation of MAC unit
      Shifter operation depend on shift_sel signal.
      ALU has 4 bit control signal for performing operation alu_sel.
      Tristate Buffer has Out_en control signal.
    • Control Unit Result
    • Conclusion
      Designed to support high-performance, repetitive, numerically intensive tasks.
      Ability to complete several accesses to memory in a single instruction cycle.
      Performance, cost, integration, ease of development, power consumption, and other factors for the application at hand.
      Datapath functions have become the dominant logic type in complex logic devices.
    • Applications
      From radar systems to consumer electronics.
      DSP data path synthesis for low-power applications.
      Application-specific function units.
    • Web Links & Information
      • Digital Logic and Microprocessor Design by Enoch O. Hwang
      • Circuit design with VHDL by Volnei A. Pedroni
      • A VHDL Primer by J. Bhasker
    • Thank You