Basic Computer Organization Chapter 2 S. Dandamudi
Outline <ul><li>Basic components </li></ul><ul><li>The processor </li></ul><ul><ul><li>Execution cycle </li></ul></ul><ul>...
Basic Components <ul><li>Basic components of a computer system </li></ul><ul><ul><li>Processor </li></ul></ul><ul><ul><li>...
Basic Components (cont’d)
The Processor <ul><li>Processor can be thought of executing  </li></ul><ul><ul><li>Fetch-decode-execute cycle forever </li...
The Processor (cont’d) <ul><li>System clock </li></ul><ul><ul><li>Provides timing signal </li></ul></ul><ul><ul><li>Clock ...
Number of Addresses <ul><li>Four categories </li></ul><ul><ul><li>3-address machines </li></ul></ul><ul><ul><ul><li>2 for ...
Number of Addresses (cont’d) <ul><li>Three-address machines </li></ul><ul><ul><li>Two for the source operands, one for the...
Number of Addresses (cont’d) <ul><li>Example </li></ul><ul><ul><li>C statement </li></ul></ul><ul><ul><ul><li>A = B + C * ...
Number of Addresses (cont’d) <ul><li>Two-address machines </li></ul><ul><ul><li>One address doubles (for source operand & ...
Number of Addresses (cont’d) <ul><li>Example </li></ul><ul><ul><li>C statement </li></ul></ul><ul><ul><ul><li>A = B + C * ...
Number of Addresses (cont’d) <ul><li>One-address machines </li></ul><ul><ul><li>Uses special set of registers called accum...
Number of Addresses (cont’d) <ul><li>Example </li></ul><ul><ul><li>C statement </li></ul></ul><ul><ul><ul><li>A = B + C * ...
Number of Addresses (cont’d) <ul><li>Zero-address machines </li></ul><ul><ul><li>Stack supplies operands and receives the ...
Number of Addresses (cont’d) <ul><li>Example </li></ul><ul><ul><li>C statement </li></ul></ul><ul><ul><ul><li>A = B + C * ...
Load/Store Architecture <ul><li>Instructions expect operands in internal processor registers </li></ul><ul><ul><li>Special...
Load/Store Architecture (cont’d) <ul><li>Sample instructions </li></ul><ul><ul><li>load  Rd,addr   ;Rd = [addr]  </li></ul...
Number of Addresses (cont’d) <ul><li>Example </li></ul><ul><ul><li>C statement </li></ul></ul><ul><ul><ul><li>A = B + C * ...
Flow of Control <ul><li>Default is sequential flow </li></ul><ul><li>Several instructions alter this default execution </l...
Flow of Control (cont’d) <ul><li>Branches </li></ul><ul><ul><li>Unconditional </li></ul></ul><ul><ul><ul><ul><li>branch  t...
Flow of Control (cont’d)
Flow of Control (cont’d) <ul><li>Branches </li></ul><ul><ul><li>Conditional </li></ul></ul><ul><ul><ul><li>Jump is taken o...
Flow of Control (cont’d) <ul><ul><ul><li>Test-and-Jump </li></ul></ul></ul><ul><ul><ul><ul><li>Single instruction performs...
Flow of Control (cont’d) <ul><li>Procedure calls </li></ul><ul><ul><li>Requires two pieces of information to return  </li>...
Flow of Control (cont’d)
Flow of Control (cont’d) <ul><li>Parameter passing </li></ul><ul><ul><li>Register-based </li></ul></ul><ul><ul><ul><li>Int...
Memory <ul><li>Memory can be viewed as an ordered sequence of bytes </li></ul><ul><li>Each byte of memory has an address <...
Memory (cont’d) <ul><li>Two basic memory operations </li></ul><ul><ul><li>Read operation (read from memory) </li></ul></ul...
Memory (cont’d) <ul><li>Steps in a typical read cycle </li></ul><ul><ul><ul><li>Place the address of the location to be re...
Memory (cont’d) <ul><li>Steps in a typical write cycle </li></ul><ul><ul><ul><li>Place the address of the location to be w...
Memory (cont’d) <ul><li>Some properties of memory </li></ul><ul><ul><li>Random access </li></ul></ul><ul><ul><ul><li>Acces...
Memory (cont’d) <ul><li>Read-only memory (ROM) </li></ul><ul><ul><ul><li>Cannot be written into this type of memory </li><...
Memory (cont’d) <ul><ul><li>Erasable PROMs (EPROMs) </li></ul></ul><ul><ul><ul><li>Can be written several times </li></ul>...
Memory (cont’d) <ul><li>Read/write memory </li></ul><ul><ul><ul><li>Commonly referred to as random access memory (RAM) </l...
Memory (cont’d) <ul><li>DRAM types </li></ul><ul><ul><li>FPM DRAMs </li></ul></ul><ul><ul><ul><li>FPM = Fast Page Mode </l...
Storing Multibyte Data
Storing Multibyte Data (cont’d) <ul><li>Little endian </li></ul><ul><ul><ul><li>Used by Intel IA-32 processors </li></ul><...
Input/Output <ul><li>I/O controller provides the necessary interface to I/O devices </li></ul><ul><ul><li>Takes care of lo...
Input/Output (cont’d) <ul><li>Processor and I/O interface points for exchanging data are called  I/O ports </li></ul><ul><...
Input/Output (cont’d) <ul><li>Pentium I/O address space </li></ul><ul><ul><li>Provides 64 KB I/O address space </li></ul><...
Performance: Data Alignment
Performance: Data Alignment (cont’d) Unaligned Aligned
Performance: Data Alignment (cont’d) <ul><li>Data alignment </li></ul><ul><ul><li>Soft alignment </li></ul></ul><ul><ul><u...
Performance: Data Alignment (cont’d) <ul><li>Data alignment requirements for byte addressable memories </li></ul><ul><ul><...
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Al2ed chapter2

  1. 1. Basic Computer Organization Chapter 2 S. Dandamudi
  2. 2. Outline <ul><li>Basic components </li></ul><ul><li>The processor </li></ul><ul><ul><li>Execution cycle </li></ul></ul><ul><ul><li>System clock </li></ul></ul><ul><li>Number of addresses </li></ul><ul><ul><li>3-address machines </li></ul></ul><ul><ul><li>2-address machines </li></ul></ul><ul><ul><li>1-address machines </li></ul></ul><ul><ul><li>0-address machines </li></ul></ul><ul><ul><li>Load/store architecture </li></ul></ul><ul><li>Flow control </li></ul><ul><ul><li>Branching </li></ul></ul><ul><ul><li>Procedure calls </li></ul></ul><ul><li>Memory </li></ul><ul><ul><li>Basic operations </li></ul></ul><ul><ul><li>Types of memory </li></ul></ul><ul><ul><li>Storing multibyte data </li></ul></ul><ul><li>Input/Output </li></ul><ul><li>Performance: Data alignment </li></ul>
  3. 3. Basic Components <ul><li>Basic components of a computer system </li></ul><ul><ul><li>Processor </li></ul></ul><ul><ul><li>Memory </li></ul></ul><ul><ul><li>I/O </li></ul></ul><ul><ul><li>System bus </li></ul></ul><ul><ul><ul><li>Address bus </li></ul></ul></ul><ul><ul><ul><li>Data bus </li></ul></ul></ul><ul><ul><ul><li>Control bus </li></ul></ul></ul>
  4. 4. Basic Components (cont’d)
  5. 5. The Processor <ul><li>Processor can be thought of executing </li></ul><ul><ul><li>Fetch-decode-execute cycle forever </li></ul></ul><ul><ul><ul><li>Fetch an instruction from the memory </li></ul></ul></ul><ul><ul><ul><li>Decode the instruction </li></ul></ul></ul><ul><ul><ul><ul><li>Find out what the operation is </li></ul></ul></ul></ul><ul><ul><ul><li>Execute the instruction </li></ul></ul></ul><ul><ul><ul><ul><li>Perform the specified operation </li></ul></ul></ul></ul>
  6. 6. The Processor (cont’d) <ul><li>System clock </li></ul><ul><ul><li>Provides timing signal </li></ul></ul><ul><ul><li>Clock period = </li></ul></ul>1 Clock frequency
  7. 7. Number of Addresses <ul><li>Four categories </li></ul><ul><ul><li>3-address machines </li></ul></ul><ul><ul><ul><li>2 for the source operands and one for the result </li></ul></ul></ul><ul><ul><li>2-address machines </li></ul></ul><ul><ul><ul><li>One address doubles as source and result </li></ul></ul></ul><ul><ul><li>1-address machine </li></ul></ul><ul><ul><ul><li>Accumulator machines </li></ul></ul></ul><ul><ul><ul><li>Accumulator is used for one source and result </li></ul></ul></ul><ul><ul><li>0-address machines </li></ul></ul><ul><ul><ul><li>Stack machines </li></ul></ul></ul><ul><ul><ul><li>Operands are taken from the stack </li></ul></ul></ul><ul><ul><ul><li>Result goes onto the stack </li></ul></ul></ul>
  8. 8. Number of Addresses (cont’d) <ul><li>Three-address machines </li></ul><ul><ul><li>Two for the source operands, one for the result </li></ul></ul><ul><ul><li>RISC processors use three addresses </li></ul></ul><ul><ul><li>Sample instructions </li></ul></ul><ul><ul><ul><li>add dest,src1,src2 </li></ul></ul></ul><ul><ul><ul><li>; M(dest)=[src1]+[src2] </li></ul></ul></ul><ul><ul><ul><li>sub dest,src1,src2 </li></ul></ul></ul><ul><ul><ul><li>; M(dest)=[src1]-[src2] </li></ul></ul></ul><ul><ul><ul><li>mult dest,src1,src2 </li></ul></ul></ul><ul><ul><ul><li>; M(dest)=[src1]*[src2] </li></ul></ul></ul>
  9. 9. Number of Addresses (cont’d) <ul><li>Example </li></ul><ul><ul><li>C statement </li></ul></ul><ul><ul><ul><li>A = B + C * D – E + F + A </li></ul></ul></ul><ul><ul><li>Equivalent code: </li></ul></ul><ul><ul><ul><li>mult T,C,D ;T = C*D </li></ul></ul></ul><ul><ul><ul><li>add T,T,B ;T = B+C*D </li></ul></ul></ul><ul><ul><ul><li>sub T,T,E ;T = B+C*D-E </li></ul></ul></ul><ul><ul><ul><li>add T,T,F ;T = B+C*D-E+F </li></ul></ul></ul><ul><ul><ul><li>add A,T,A ;A = B+C*D-E+F+A </li></ul></ul></ul>
  10. 10. Number of Addresses (cont’d) <ul><li>Two-address machines </li></ul><ul><ul><li>One address doubles (for source operand & result) </li></ul></ul><ul><ul><li>Last example makes a case for it </li></ul></ul><ul><ul><ul><li>Address T is used twice </li></ul></ul></ul><ul><ul><li>Sample instructions </li></ul></ul><ul><ul><li>load dest,src ; M(dest)=[src] </li></ul></ul><ul><ul><li>add dest,src ; M(dest)=[dest]+[src] </li></ul></ul><ul><ul><li>sub dest,src ; M(dest)=[dest]-[src] </li></ul></ul><ul><ul><li>mult dest,src ; M(dest)=[dest]*[src] </li></ul></ul>
  11. 11. Number of Addresses (cont’d) <ul><li>Example </li></ul><ul><ul><li>C statement </li></ul></ul><ul><ul><ul><li>A = B + C * D – E + F + A </li></ul></ul></ul><ul><ul><li>Equivalent code: </li></ul></ul><ul><ul><ul><li>load T,C ;T = C </li></ul></ul></ul><ul><ul><ul><li>mult T,D ;T = C*D </li></ul></ul></ul><ul><ul><ul><li>add T,B ;T = B+C*D </li></ul></ul></ul><ul><ul><ul><li>sub T,E ;T = B+C*D-E </li></ul></ul></ul><ul><ul><ul><li>add T,F ;T = B+C*D-E+F </li></ul></ul></ul><ul><ul><ul><li>add A,T ;A = B+C*D-E+F+A </li></ul></ul></ul>
  12. 12. Number of Addresses (cont’d) <ul><li>One-address machines </li></ul><ul><ul><li>Uses special set of registers called accumulators </li></ul></ul><ul><ul><ul><li>Specify one source operand & receive the result </li></ul></ul></ul><ul><ul><li>Called accumulator machines </li></ul></ul><ul><ul><li>Sample instructions </li></ul></ul><ul><ul><li>load addr ; accum = [addr] </li></ul></ul><ul><ul><li>store addr ; M[addr] = accum </li></ul></ul><ul><ul><li>add addr ; accum = accum + [addr] </li></ul></ul><ul><ul><li>sub addr ; accum = accum - [addr] </li></ul></ul><ul><ul><li>mult addr ; accum = accum * [addr] </li></ul></ul>
  13. 13. Number of Addresses (cont’d) <ul><li>Example </li></ul><ul><ul><li>C statement </li></ul></ul><ul><ul><ul><li>A = B + C * D – E + F + A </li></ul></ul></ul><ul><ul><li>Equivalent code: </li></ul></ul><ul><ul><ul><li>load C ;load C into accum </li></ul></ul></ul><ul><ul><ul><li>mult D ;accum = C*D </li></ul></ul></ul><ul><ul><ul><li>add B ;accum = C*D+B </li></ul></ul></ul><ul><ul><ul><li>sub E ;accum = B+C*D-E </li></ul></ul></ul><ul><ul><ul><li>add F ;accum = B+C*D-E+F </li></ul></ul></ul><ul><ul><ul><li>add A ;accum = B+C*D-E+F+A </li></ul></ul></ul><ul><ul><ul><li>store A ;store accum contents in A </li></ul></ul></ul>
  14. 14. Number of Addresses (cont’d) <ul><li>Zero-address machines </li></ul><ul><ul><li>Stack supplies operands and receives the result </li></ul></ul><ul><ul><ul><li>Special instructions to load and store use an address </li></ul></ul></ul><ul><ul><li>Called stack machines (Ex: HP3000, Burroughs B5500) </li></ul></ul><ul><ul><li>Sample instructions </li></ul></ul><ul><ul><li>push addr ; push([addr]) </li></ul></ul><ul><ul><li>pop addr ; pop([addr]) </li></ul></ul><ul><ul><li>add ; push(pop + pop) </li></ul></ul><ul><ul><li>sub ; push(pop - pop) </li></ul></ul><ul><ul><li>mult ; push(pop * pop) </li></ul></ul>
  15. 15. Number of Addresses (cont’d) <ul><li>Example </li></ul><ul><ul><li>C statement </li></ul></ul><ul><ul><ul><li>A = B + C * D – E + F + A </li></ul></ul></ul><ul><ul><li>Equivalent code: </li></ul></ul><ul><ul><ul><li>push E sub </li></ul></ul></ul><ul><ul><ul><li>push C push F </li></ul></ul></ul><ul><ul><ul><li>push D add </li></ul></ul></ul><ul><ul><ul><li>Mult push A </li></ul></ul></ul><ul><ul><ul><li>push B add </li></ul></ul></ul><ul><ul><ul><li>add pop A </li></ul></ul></ul>
  16. 16. Load/Store Architecture <ul><li>Instructions expect operands in internal processor registers </li></ul><ul><ul><li>Special LOAD and STORE instructions move data between registers and memory </li></ul></ul><ul><ul><li>RISC and vector processors use this architecture </li></ul></ul><ul><ul><li>Reduces instruction length </li></ul></ul>
  17. 17. Load/Store Architecture (cont’d) <ul><li>Sample instructions </li></ul><ul><ul><li>load Rd,addr ;Rd = [addr] </li></ul></ul><ul><ul><li>store addr,Rs ;(addr) = Rs </li></ul></ul><ul><ul><li>add Rd,Rs1,Rs2 ;Rd = Rs1 + Rs2 </li></ul></ul><ul><ul><li>sub Rd,Rs1,Rs2 ;Rd = Rs1 - Rs2 </li></ul></ul><ul><ul><li>mult Rd,Rs1,Rs2 ;Rd = Rs1 * Rs2 </li></ul></ul>
  18. 18. Number of Addresses (cont’d) <ul><li>Example </li></ul><ul><ul><li>C statement </li></ul></ul><ul><ul><ul><li>A = B + C * D – E + F + A </li></ul></ul></ul><ul><ul><li>Equivalent code: </li></ul></ul><ul><ul><ul><li>load R1,B mult R2,R2,R3 </li></ul></ul></ul><ul><ul><ul><li>load R2,C add R2,R2,R1 </li></ul></ul></ul><ul><ul><ul><li>load R3,D sub R2,R2,R4 </li></ul></ul></ul><ul><ul><ul><li>load R4,E add R2,R2,R5 </li></ul></ul></ul><ul><ul><ul><li>load R5,F add R2,R2,R6 </li></ul></ul></ul><ul><ul><ul><li>load R6,A store A,R2 </li></ul></ul></ul>
  19. 19. Flow of Control <ul><li>Default is sequential flow </li></ul><ul><li>Several instructions alter this default execution </li></ul><ul><ul><li>Branches </li></ul></ul><ul><ul><ul><li>Unconditional </li></ul></ul></ul><ul><ul><ul><li>Conditional </li></ul></ul></ul><ul><ul><li>Procedure calls </li></ul></ul><ul><ul><ul><li>Parameter passing </li></ul></ul></ul><ul><ul><ul><ul><li>Register-based </li></ul></ul></ul></ul><ul><ul><ul><ul><li>Stack-based </li></ul></ul></ul></ul>
  20. 20. Flow of Control (cont’d) <ul><li>Branches </li></ul><ul><ul><li>Unconditional </li></ul></ul><ul><ul><ul><ul><li>branch target </li></ul></ul></ul></ul><ul><ul><ul><li>Absolute address </li></ul></ul></ul><ul><ul><ul><li>PC-relative </li></ul></ul></ul><ul><ul><ul><ul><li>Target address is specified relative to PC contents </li></ul></ul></ul></ul><ul><ul><li>Example: MIPS </li></ul></ul><ul><ul><ul><li>Absolute address </li></ul></ul></ul><ul><ul><ul><ul><li>j target </li></ul></ul></ul></ul><ul><ul><ul><li>PC-relative </li></ul></ul></ul><ul><ul><ul><ul><li>b target </li></ul></ul></ul></ul>
  21. 21. Flow of Control (cont’d)
  22. 22. Flow of Control (cont’d) <ul><li>Branches </li></ul><ul><ul><li>Conditional </li></ul></ul><ul><ul><ul><li>Jump is taken only if the condition is met </li></ul></ul></ul><ul><ul><li>Two types </li></ul></ul><ul><ul><ul><li>Set-Then-Jump </li></ul></ul></ul><ul><ul><ul><ul><li>Condition testing is separated from branching </li></ul></ul></ul></ul><ul><ul><ul><ul><li>Condition code registers are used to convey the condition test result </li></ul></ul></ul></ul><ul><ul><ul><li>Example: Pentium code </li></ul></ul></ul><ul><ul><ul><ul><li>cmp AX,BX </li></ul></ul></ul></ul><ul><ul><ul><ul><li>je target </li></ul></ul></ul></ul>
  23. 23. Flow of Control (cont’d) <ul><ul><ul><li>Test-and-Jump </li></ul></ul></ul><ul><ul><ul><ul><li>Single instruction performs condition testing and branching </li></ul></ul></ul></ul><ul><ul><ul><li>Example: MIPS instruction </li></ul></ul></ul><ul><ul><ul><ul><li>beq Rsrc1,Rsrc2,target </li></ul></ul></ul></ul><ul><ul><ul><ul><ul><li>Jumps to target if Rsrc1 = Rsrc2 </li></ul></ul></ul></ul></ul>
  24. 24. Flow of Control (cont’d) <ul><li>Procedure calls </li></ul><ul><ul><li>Requires two pieces of information to return </li></ul></ul><ul><ul><ul><li>End of procedure </li></ul></ul></ul><ul><ul><ul><ul><li>Pentium </li></ul></ul></ul></ul><ul><ul><ul><ul><ul><li>uses ret instruction </li></ul></ul></ul></ul></ul><ul><ul><ul><ul><li>MIPS </li></ul></ul></ul></ul><ul><ul><ul><ul><ul><li>uses jr instruction </li></ul></ul></ul></ul></ul><ul><ul><ul><li>Return address </li></ul></ul></ul><ul><ul><ul><ul><li>In a (special) register </li></ul></ul></ul></ul><ul><ul><ul><ul><ul><li>MIPS allows any general-purpose register </li></ul></ul></ul></ul></ul><ul><ul><ul><ul><li>On the stack </li></ul></ul></ul></ul><ul><ul><ul><ul><ul><li>Pentium </li></ul></ul></ul></ul></ul>
  25. 25. Flow of Control (cont’d)
  26. 26. Flow of Control (cont’d) <ul><li>Parameter passing </li></ul><ul><ul><li>Register-based </li></ul></ul><ul><ul><ul><li>Internal registers are used </li></ul></ul></ul><ul><ul><ul><ul><li>Faster </li></ul></ul></ul></ul><ul><ul><ul><ul><li>Limit the number of parameters </li></ul></ul></ul></ul><ul><ul><ul><ul><ul><li>Due to limited number of available registers </li></ul></ul></ul></ul></ul><ul><ul><li>Stack-based </li></ul></ul><ul><ul><ul><li>Stack is used </li></ul></ul></ul><ul><ul><ul><ul><li>Slower </li></ul></ul></ul></ul><ul><ul><ul><ul><li>Requires memory access </li></ul></ul></ul></ul><ul><ul><ul><ul><li>General-purpose </li></ul></ul></ul></ul><ul><ul><ul><ul><ul><li>Not limited by the number of registers </li></ul></ul></ul></ul></ul>
  27. 27. Memory <ul><li>Memory can be viewed as an ordered sequence of bytes </li></ul><ul><li>Each byte of memory has an address </li></ul><ul><ul><li>Memory address is essentially the sequence number of the byte </li></ul></ul><ul><ul><li>Such memories are called byte addressable </li></ul></ul><ul><ul><li>Number of address lines determine the memory address space of a processor </li></ul></ul>
  28. 28. Memory (cont’d) <ul><li>Two basic memory operations </li></ul><ul><ul><li>Read operation (read from memory) </li></ul></ul><ul><ul><li>Write operation (write into memory) </li></ul></ul><ul><li>Access time </li></ul><ul><ul><ul><li>Time needed to retrieve data at addressed location </li></ul></ul></ul><ul><li>Cycle time </li></ul><ul><ul><ul><li>Minimum time between successive operations </li></ul></ul></ul>
  29. 29. Memory (cont’d) <ul><li>Steps in a typical read cycle </li></ul><ul><ul><ul><li>Place the address of the location to be read on the address bus </li></ul></ul></ul><ul><ul><ul><li>Activate the memory read control signal on the control bus </li></ul></ul></ul><ul><ul><ul><li>Wait for the memory to retrieve the data from the addressed memory location </li></ul></ul></ul><ul><ul><ul><li>Read the data from the data bus </li></ul></ul></ul><ul><ul><ul><li>Drop the memory read control signal to terminate the read cycle </li></ul></ul></ul><ul><ul><li>A simple Pentium memory read cycle takes 3 clocks </li></ul></ul><ul><ul><ul><ul><li>Steps 1&2 and 4&5 are done in one clock cycle each </li></ul></ul></ul></ul><ul><ul><li>For slower memories, wait cycles will have to be inserted </li></ul></ul>
  30. 30. Memory (cont’d) <ul><li>Steps in a typical write cycle </li></ul><ul><ul><ul><li>Place the address of the location to be written on the address bus </li></ul></ul></ul><ul><ul><ul><li>Place the data to be written on the data bus </li></ul></ul></ul><ul><ul><ul><li>Activate the memory write control signal on the control bus </li></ul></ul></ul><ul><ul><ul><li>Wait for the memory to store the data at the addressed location </li></ul></ul></ul><ul><ul><ul><li>Drop the memory write control signal to terminate the write cycle </li></ul></ul></ul><ul><ul><li>A simple Pentium memory write cycle takes 3 clocks </li></ul></ul><ul><ul><ul><ul><li>Steps 1&3 and 4&5 are done in one clock cycle each </li></ul></ul></ul></ul><ul><ul><li>For slower memories, wait cycles will have to be inserted </li></ul></ul>
  31. 31. Memory (cont’d) <ul><li>Some properties of memory </li></ul><ul><ul><li>Random access </li></ul></ul><ul><ul><ul><li>Accessing any memory location takes the same amount of time </li></ul></ul></ul><ul><ul><li>Volatility </li></ul></ul><ul><ul><ul><li>Volatile memory </li></ul></ul></ul><ul><ul><ul><ul><li>Needs power to retain the contents </li></ul></ul></ul></ul><ul><ul><ul><li>Non-volatile memory </li></ul></ul></ul><ul><ul><ul><ul><li>Retains contents even in the absence of power </li></ul></ul></ul></ul><ul><li>Basic types of memory </li></ul><ul><ul><li>Read-only memory (ROM) </li></ul></ul><ul><ul><li>Read/write memory (RAM) </li></ul></ul>
  32. 32. Memory (cont’d) <ul><li>Read-only memory (ROM) </li></ul><ul><ul><ul><li>Cannot be written into this type of memory </li></ul></ul></ul><ul><ul><ul><li>Non-volatile memory </li></ul></ul></ul><ul><ul><ul><li>Most are factory programmed (i.e., written) </li></ul></ul></ul><ul><ul><li>Programmable ROMs (PROMs) </li></ul></ul><ul><ul><ul><li>Can be written once by user </li></ul></ul></ul><ul><ul><ul><ul><li>A fuse is associated with each bit cell </li></ul></ul></ul></ul><ul><ul><ul><ul><li>Special equipment is needed to write (to blow the fuse) </li></ul></ul></ul></ul><ul><ul><ul><li>PROMS are useful </li></ul></ul></ul><ul><ul><ul><ul><li>During prototype development </li></ul></ul></ul></ul><ul><ul><ul><ul><li>If the required quantity is small </li></ul></ul></ul></ul><ul><ul><ul><ul><ul><li>Does not justify the cost of factory programmed ROM </li></ul></ul></ul></ul></ul>
  33. 33. Memory (cont’d) <ul><ul><li>Erasable PROMs (EPROMs) </li></ul></ul><ul><ul><ul><li>Can be written several times </li></ul></ul></ul><ul><ul><ul><li>Offers further flexibility during system prototyping </li></ul></ul></ul><ul><ul><ul><li>Can be erased by exposing to ultraviolet light </li></ul></ul></ul><ul><ul><ul><ul><li>Cannot erase contents of selected locations </li></ul></ul></ul></ul><ul><ul><ul><ul><ul><li>All contents are lost </li></ul></ul></ul></ul></ul><ul><ul><li>Electrically erasable PROMs (EEPROMs) </li></ul></ul><ul><ul><ul><li>Contents are electrically erased </li></ul></ul></ul><ul><ul><ul><li>No need to erase all contents </li></ul></ul></ul><ul><ul><ul><ul><li>Typically a subset of the locations are erased as a group </li></ul></ul></ul></ul><ul><ul><ul><ul><li>Most EEPROMs do not provide the capability to individually erase contents of a single location </li></ul></ul></ul></ul>
  34. 34. Memory (cont’d) <ul><li>Read/write memory </li></ul><ul><ul><ul><li>Commonly referred to as random access memory (RAM) </li></ul></ul></ul><ul><ul><ul><li>Volatile memories </li></ul></ul></ul><ul><ul><li>Two basic types </li></ul></ul><ul><ul><ul><li>Static RAM (SRAM) </li></ul></ul></ul><ul><ul><ul><ul><li>Retains data with no further maintenance </li></ul></ul></ul></ul><ul><ul><ul><ul><li>Typically used for CPU registers and cache memory </li></ul></ul></ul></ul><ul><ul><ul><li>Dynamic RAM (DRAM) </li></ul></ul></ul><ul><ul><ul><ul><li>A tiny capacitor is used to store a bit </li></ul></ul></ul></ul><ul><ul><ul><ul><li>Due to leakage of charge, DRAMs must be refreshed to retain contents </li></ul></ul></ul></ul><ul><ul><ul><ul><li>Read operation is destructive in DRAMs </li></ul></ul></ul></ul>
  35. 35. Memory (cont’d) <ul><li>DRAM types </li></ul><ul><ul><li>FPM DRAMs </li></ul></ul><ul><ul><ul><li>FPM = Fast Page Mode </li></ul></ul></ul><ul><ul><li>EDO DRAMs </li></ul></ul><ul><ul><ul><li>EDO = Extended Data Out </li></ul></ul></ul><ul><ul><ul><ul><li>Uses pipelining to speedup access </li></ul></ul></ul></ul><ul><ul><li>SDRAMs </li></ul></ul><ul><ul><ul><li>Use an external clock to synchronize data output </li></ul></ul></ul><ul><ul><ul><li>Also called SDR SDRAMs (Single Data Rate) </li></ul></ul></ul><ul><ul><li>DDR SDRAMs </li></ul></ul><ul><ul><ul><li>DDR = Double Data Rate </li></ul></ul></ul><ul><ul><ul><li>Provides data on both falling and rising edges of the clock </li></ul></ul></ul><ul><ul><li>RDRAMs </li></ul></ul><ul><ul><ul><li>Rambus DRAM </li></ul></ul></ul>
  36. 36. Storing Multibyte Data
  37. 37. Storing Multibyte Data (cont’d) <ul><li>Little endian </li></ul><ul><ul><ul><li>Used by Intel IA-32 processors </li></ul></ul></ul><ul><li>Big endian </li></ul><ul><ul><ul><li>Used most processors by default </li></ul></ul></ul><ul><li>MIPS supports both byte orderings </li></ul><ul><ul><ul><li>Big endian is the default </li></ul></ul></ul><ul><li>Not a problem when working with same type of machines </li></ul><ul><ul><ul><li>Need to convert the format if working with a different machine </li></ul></ul></ul><ul><ul><ul><li>Pentium provides two instructions for conversion </li></ul></ul></ul><ul><ul><ul><ul><li>xchg for 16-bit data </li></ul></ul></ul></ul><ul><ul><ul><ul><li>bswap for 32-bit data </li></ul></ul></ul></ul>
  38. 38. Input/Output <ul><li>I/O controller provides the necessary interface to I/O devices </li></ul><ul><ul><li>Takes care of low-level, device-dependent details </li></ul></ul><ul><ul><li>Provides necessary electrical signal interface </li></ul></ul>
  39. 39. Input/Output (cont’d) <ul><li>Processor and I/O interface points for exchanging data are called I/O ports </li></ul><ul><li>Two ways of mapping I/O ports </li></ul><ul><ul><li>Memory-mapped I/O </li></ul></ul><ul><ul><ul><li>I/O ports are mapped to the memory address space </li></ul></ul></ul><ul><ul><ul><ul><li>Reading/writing I/O is similar to reading/writing memory </li></ul></ul></ul></ul><ul><ul><ul><ul><ul><li>Can use memory read/write instructions </li></ul></ul></ul></ul></ul><ul><ul><ul><li>Motorola 68000 uses memory-mapped I/O </li></ul></ul></ul><ul><ul><li>Isolated I/O </li></ul></ul><ul><ul><ul><li>Separate I/O address space </li></ul></ul></ul><ul><ul><ul><li>Requires special I/O instructions (like in and out in Pentium) </li></ul></ul></ul><ul><ul><ul><li>Intel 80x86 processors support isolated I/O </li></ul></ul></ul>
  40. 40. Input/Output (cont’d) <ul><li>Pentium I/O address space </li></ul><ul><ul><li>Provides 64 KB I/O address space </li></ul></ul><ul><ul><li>Can be used for 8-, 16-, and 32-bit I/O ports </li></ul></ul><ul><ul><li>Combination cannot exceed the total I/O address space </li></ul></ul><ul><ul><ul><li>can have 64 K 8-bit ports </li></ul></ul></ul><ul><ul><ul><li>can have 32 K 16-bit ports </li></ul></ul></ul><ul><ul><ul><li>can have 16 K 32-bit ports </li></ul></ul></ul><ul><ul><ul><li>A combination of these for a total of 64 KB </li></ul></ul></ul><ul><ul><li>I/O instructions do not go through segmentation or paging </li></ul></ul><ul><ul><ul><li>I/O address refers to the physical I/O address </li></ul></ul></ul>
  41. 41. Performance: Data Alignment
  42. 42. Performance: Data Alignment (cont’d) Unaligned Aligned
  43. 43. Performance: Data Alignment (cont’d) <ul><li>Data alignment </li></ul><ul><ul><li>Soft alignment </li></ul></ul><ul><ul><ul><li>Data is not required to be aligned </li></ul></ul></ul><ul><ul><ul><ul><li>Data alignment is optional </li></ul></ul></ul></ul><ul><ul><ul><ul><ul><li>Aligned data gives better performance </li></ul></ul></ul></ul></ul><ul><ul><ul><li>Used in Intel IA-32 processors </li></ul></ul></ul><ul><ul><li>Hard alignment </li></ul></ul><ul><ul><ul><li>Data must be aligned </li></ul></ul></ul><ul><ul><ul><li>Used in Motorola 680X0 and Intel i860 processors </li></ul></ul></ul>
  44. 44. Performance: Data Alignment (cont’d) <ul><li>Data alignment requirements for byte addressable memories </li></ul><ul><ul><li>1-byte data </li></ul></ul><ul><ul><ul><li>Always aligned </li></ul></ul></ul><ul><ul><li>2-byte data </li></ul></ul><ul><ul><ul><li>Aligned if the data is stored at an even address (i.e., at an address that is a multiple of 2) </li></ul></ul></ul><ul><ul><li>4-byte data </li></ul></ul><ul><ul><ul><li>Aligned if the data is stored at an address that is a multiple of 4 </li></ul></ul></ul><ul><ul><li>8-byte data </li></ul></ul><ul><ul><ul><li>Aligned if the data is stored at an address that is a multiple of 8 </li></ul></ul></ul>Last slide
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