vlsi report


Published on

Published in: Education, Technology, Business
  • Be the first to comment

No Downloads
Total views
On SlideShare
From Embeds
Number of Embeds
Embeds 0
No embeds

No notes for slide

vlsi report

  1. 1. GURGAON COLLEGE OF ENGINEERING INDUSTRIAL INTERNSHIP REPORT Undertaken at SSPL, DRDO (Defense Research & Development Organization) June 7th2011-july 31st 2011 ON THE TOPIC OF “INTRODUCTION OF PHOTOLITHOGRAPHY AND STUDY OF METALLIZATION IN GaAs”Under the Supervisors: Submitted by:Ms. Seema Vinayak Aayush BhatnagarScientist F (Electronics & Comm.Engg)Mr. Robert Laishram 4nd YearScientist D 0803001
  2. 2. INTRODUCTION OF PHOTOLITHOGRAPHYAND STUDY OF METALLIZATION IN GaAs Submitted by: - NAME :- AAYUSH BHATNAGAR ROLL NO :- 0803001 In partial fulfillment of requirements for the award of the degree of B.TECH (Electronics and communication), GURGAON COLLEGE OF ENGINEERING Summer training JUNE 7th 2011-JULY 31ST 2011 Supervisors Ms. Seema Vinayak Mr. RobertLaishram Scientist F Scientist D Project undertaken at Solid State Physics Laboratory(SSPL) Defence Research and Development Organisation(DRDO) Lucknow Road Timarpur , Delhi - 110054
  3. 3. ACKNOWLEDGEMENT I am deeply intended to Dr R Murlidharan, Director, Solid State Physics Laboratory, Lucknowroad, Delhi for providing me the opportunity to work on project ―INTRODUCTION OFPHOTOLITHOGRAPHY AND STUDY OF METALLIZATION IN GaAs ― as part of myB.TECH (Electronics and communication) curriculum.My special thanks to Ms. SEEMA VINAYAK, Scientist (F), my in charge for her constant supportand guidance .I strongly record my deep sense of gratitude and thankfulness with utmost respectto my project guide Mr. ROBERT LAISHRAM, Scientist (D), for providing me with valuableinformation and help without which this project would not have been a success.I am thankful to Mr. D.S. RAWAL , Scientist (F) ,Mr. A. NAYAK ,Scientist (F),Mr. and Mr.RUPESH SIR ,SCIENTIST (D) and Ms. Henalika, Scientist (D) without their continuousguidance and support; this project would not have been possible.Again I shall be thankful to all the department members for providing me thesame opportunity.
  4. 4. ABSTRACTThis report basically deals with the fabrication of GaAs ,technique used for it andmetallization of GaAs.First there is a brief idea about the MMIC ,what are they and why they are used, Differencebetween two families of electronic devices.Mid section of report deals with fabrication of GaAs , lithography and its typesLatter part contain metallization technique ,types of contacts and difference between differenttechniques.
  5. 5. Table of content  Introduction  Chapter -1 DRDO  SSPL  Chapter -2 MMIC  Fabrication of MMIC  chapter- 3 Electronic devices (transistor) Family  Difference Between BJT and FET  differences  chapter- 4 GaAs  Comparison with silicon  GaAs advantages  Silicon advantages over GaAs  CHAPTER-5 LITHOGRAPHY  Photolithography a) Wafer Cleaning, Barrier Formation and PhotoresistApplication b) Soft-Baking c) Alignment d) Mask Alignment and Exposure 1. Contact Printing 2. Proximity Printing 3. Projection Printing e) Development f) Hard-Baking
  6. 6. g) Etching 1. Wet etching 2. Plasma etching  OVERALL PROCEDURE  Photoresists  Lift off  Etching CHAPTER-5 Metallization 1) Ohmic contacts 2) Schottky Contact  Techniques of metallization  Physical vapor deposition  Sputtering Conclusion Bibliography
  7. 7. INTRODUCTIONThis basically deals with the GaAs as fabrication material of future ICs. The GaAs is profoundlyused in the various application of defense. GaAs has various advantages over silicon because ofthese advantages it is preferred over silicon.I have done my summer training in Solid State Physical Laboratory(SSPL) where I deal with thefabrication of GaAs and its various process.Some of the instrument I used in training includes Surface Profiler, Dektak , Curve Tracer,Automatic Photolithography Machine etc.Report is divided into 5 chapters :-Chapter-1:DRDOChapter-2:MMICChapter-3:Electronic devices (transistor) FamilyChapter-4:GaAsChapter-5:LithogrophyChapter-6:Metallization
  8. 8. Chapter -1DRDODRDO (Defence Research & Development Organization) was formed in 1958 fromthe amalgamation of the then already functioning Technical DevelopmentEstablishment (TDEs) of the Indian Army and the Directorate of TechnicalDevelopment & Production (DTDP) with the Defence Science Organization (DSO).DRDO was then a small organization with 10 establishments or laboratories. Over the years, ithas grown multi-directionally in terms of the variety of subject disciplines, number oflaboratories, achievements and stature.Today, DRDO is a network of 51 laboratories which are deeply engaged indeveloping defence technologies covering various disciplines, like aeronautics,armaments, electronics, combat vehicles, engineering systems, instrumentation,missiles, advanced computing and simulation, special materials, naval systems,lifesciences,training, information systemsand agriculture.Presently, the Organization is backed by over 5000 scientists and about 25,000 other scientific,technical and supporting personnel.Several major projects for the development of missiles, armaments, light combat aircrafts,radars, electronic warfare systems etc are on hand and significant achievements havealready been made in several such technologies.DRDO - VisionMake India prosperous by establishing world class science and technology base and provide ourDefence Services decisive edge by equipping them with internationally competitive systems andsolutions.
  9. 9. DRDO - MissionDesign, develop and lead to production state-of-the-art sensors, weaponsystems, platforms and allied equipment for our Defence Services. rovide technological solutions to the Services to optimise combat Peffectiveness and to promote well-being of the troops.Develop infrastructure and committed quality manpower and build strongindigenous technology base.
  10. 10. SSPL Figure 1Solid State Physics Laboratory (sspl), one of the establishments under theDEFENCE RESEARCH AND DEVELOPMENT ORGANISATION (DRDO),Ministry of Defence, was established in 1962 with the broad objective ofdeveloping an R&D base in the field of Solid State Materials, Devices and Sub-systems.The Laboratory has a vision to be the centre of excellence in the development ofSolid State Materials, Devices and has a Mission to develop and characterizehigh purity materials and solid state devices and to enhance infrastructure,technology for meeting the futuristic challenges.ACHIEVEMENTSThe Laboratory has contributed immensely on the growth of materials anddevelopment of devices. Some of the achievements are: SPST Switch GaAs MMIC technology Remotely activated acoustic warning system (RAAWS) Silicon Photo diodes & Silicon Quadrant Detectors GaAs Gunn Diodes for W-band applications Thermo – Electric Coolers
  11. 11. AREAS OF WORKOver the years, the Laboratory has developed core competence in the design anddevelopment in the following areas:- GaAs based Microwave devices and circuits SAW devices & sensors MEMs components IR devices and Materials Development & Characterization
  12. 12. CHAPTER-2 MMICA Monolithic Microwave Integrated Circuit, or MMIC (sometimes pronounced"mimic"), is a type of integrated circuit (IC) device that operates at microwavefrequencies (300 MHz to 300 GHz). These devices typically perform functionssuch as microwave mixing, power amplification, low noise amplification, andhigh frequency switching. Inputs and outputs on MMIC devices are frequentlymatched to a characteristic impedance of 50 ohms. This makes them easier to use,as cascading of MMICs does not then require an external matching network.Additionally most microwave test equipment is designed to operate in a 50 ohmenvironment.MMICs are dimensionally small (from around 1 mm² to 10 mm²) and can bemass produced, which has allowed the proliferation of high frequency devicessuch as cellular phones. MMICs were originally fabricated using gallium arsenide(GaAs), an III-V compound semiconductor. It has two fundamental advantagesover Silicon (Si), the traditional material for IC realization: device (transistor)speed and a semi-insulating substrate. Both factors help with the design of highfrequency circuit functions. However, the speed of Si-based technologies hasgradually increased as transistor feature sizes have reduced and MMICs can nowalso be fabricated in Si technology. The primary advantage of Si technology is itslower fabrication cost compared with GaAs. GaAs has high speed, largebandwidth, high saturated drift velocity, more radiation resistance, low noise.
  13. 13. Fabrication of MMICIt includes following steps :- Wafer processing o Wet cleans o Photolithography o Ion implantation (in which dopants are embedded in the wafer creating regions of increased (or decreased conductivity) o Etching: dry and wet o Thermal treatments : Rapid thermal anneal and Thermal oxidation o vapour deposition : a. physical and chemical b. Molecular beam epitaxy (MBE) c. Chemical-mechanical planarization (CMP) d. Wafer testing (where the electrical performance is verified) IC packaging o Die attachment o IC Bonding : a. Wire bonding b. Wafer bonding c. Tab bonding o IC encapsulation : Baking, Plating, Laser marking, Trim and form IC testing
  14. 14. CHAPTER-3Electronic devices (transistor) FamilyFlowchart Electronic devices (transistor) Bipolar Unipolar HeterojunctionHomojunction Homojunction Heterojunction bipolar(BJT) FET FET transistor (HBT) MESFET MOSFET HEMT JFET HIGFET Figure-2
  15. 15. Difference Between BJT and FETBJT vs FETBoth BJT (Bipolar Junction Transistor) and FET (Field Effect Transistor) are twotypes of transistors. Transistor is an electronic semiconductor device that gives alargely changing electrical output signal for small changes in small input signals.Due to this quality, the device can be used as either an amplifier or a switch.Transistor was released in 1950s and it can be considered as one of the mostimportant invention in 20th century considering its contribution to thedevelopment of IT. Different types of architectures for transistor have beentested.Bipolar Junction Transistor (BJT)BJT is consists of two PN junctions (a junction made by connecting a p typesemiconductor and n type semiconductor). These two junctions are formed usingconnecting three semiconductor pieces in the order of P-N-P or N-P-N. There fortwo types of BJTs known as PNP and NPN are available.Three electrodes are connected to these three semiconductor parts and middle leadis called ‘base’. Other two junctions are ‘emitter’ and ‘collector’.In BJT, large collector emitter (IC) current is controlled by the small base emittercurrent (IB) and this property is exploited to design amplifiers or switches. Therefor it can be considered as a current driven device. BJT is mostly used in amplifiercircuits.Field Effect Transistor (FET)FET is made of three terminals known as ‘Gate’, ‘Source’ and ‘Drain’. Heredrain current is controlled by the gate voltage. Therefore, FETs are voltagecontrolled devices.Depending on the type of semiconductor used for source and drain (in FET bothof them are made of the same semiconductor type), a FET can be an N channelor P channel device. Source to drain current flow is controlled by adjusting thechannel width by applying an appropriate voltage to gate. There are also twoways of controlling the channel width known as depletion and enhancement.Therefore FETs are available in four different types such as N channel or P
  16. 16. channel with either in depletion or enhancement mode.There are many types of FETs such as MOSFET (Metal Oxide SemiconductorFET), HEMT (High Electron Mobility Transistor) and IGBT (Insulated GateBipolar Transistor). CNTFET (Carbon Nanotube FET) which was resulted bythe development of nanotechnology is the latest member of FET family.Differences1. BJT is basically a current driven device, though FET is considered as avoltage controlled device.2. Terminals of BJT are known as emitter, collector and base, whereas FET ismade of gate, source and drain.3. In most of the new applications, FETs are used than BJTs.4. BJT uses both electrons and holes for conduction, whereas FET uses only oneof them and hence referred to as unipolar transistors.5. FETs are power efficient than BJTs.
  17. 17. CHAPTER-4GaAsGallium arsenide (GaAs) is a compound of the elements gallium and arsenic. Itis a III/Vsemiconductor, and is used in the manufacture of devices such asmicrowave frequencyintegrated circuits, monolithic microwave integratedcircuits, infrared light-emitting diodes, laser diodes, solar cells, and opticalwindows. Figure-3Comparison with siliconGaAs advantages 1. It has a higher saturated electron velocity and higher electron mobility, allowing transistors made from it to function at frequencies in excess of 250 GHz. 2. Unlike silicon junctions, GaAs devices are relatively insensitive to heat due to their higher bandgap. 3. GaAs devices tend to have less noise than silicon devices especially at high frequencies which is a result of higher carrier mobilities and lower resistive device parasitics. These properties recommend GaAs circuitry in mobile phones, satellite communications, microwave point-to-point links, and higher frequency radarsystems. It is used in the manufacture of Gunn diodes for generation of microwaves. 4. GaAs has a direct band gap, which means that it can be used to emit light efficiently. Silicon has an indirect bandgap and so is very poor at emitting light. Due to its lower bandgap though, Si LEDs can not emit
  18. 18. visible light and rather work in IR range while GaAs LEDs function in visible red light. 5. As a wide direct band gap material and resulting resistance to radiation damage, GaAs is an excellent material for space electronics and optical windows in high power applications.Because of its wide bandgap, pure GaAs is highly resistive. 6. Combined with the high dielectric constant, this property makes GaAs a very good electrical substrate and unlike Si provides natural isolation between devices and circuits. This has made it an ideal material for microwave and millimeter wave integrated circuits, MMICs, where active and essential passive components can readily be produced on a single slice of GaAs.Silicon advantages over GaAsSilicon has three major advantages over GaAs for integrated circuitmanufacture. 1. silicon is abundant and cheap to process. Si is highly abundant in the Earths crust, in the form of silicate minerals. The economy of scale available to the silicon industry has also reduced the adoption of GaAs. 2. a Si crystal has an extremely stable structure mechanically and it can be grown to very large diameter boules and can be processed with very high yields. It is also a decent thermal conductor thus enable very dense packing of transistors, all very desirable for design and manufacturing of very large ICs. Such good mechanical characteristics also make it a suitable material for the rapidly developing field of nanoelectronics. 3. The major advantage of Si is the existence of silicon dioxide—one of the best insulators. Silicon dioxide can easily be incorporated onto silicon circuits, and such layers are adherent to the underlying Si. GaAs does not easily form such a stable adherent insulating layer and does not have stable oxide either. 4. The perhaps most important, advantage of silicon is that it possesses a much higher hole mobility. This high mobility allows the fabrication of higher-speed P-channel field effect transistors, which are required for CMOS logic. Because they lack a fast CMOS structure, GaAs logic circuits have much higher power consumption, which has made them unable to compete with silicon logic circuits.
  19. 19. CHAPTER-5LITHOGRAPHYLithography (from Greek λίθος - lithos, stone + γράφειν - graphein, to write)It is a general name given to processes used to transfer patterns on to a substrateto define structures that make up devices.Types of lithography:(a) Photolithography (or optical lithography) uses UV radiation.(b) X-ray lithography uses X-ray.(c) Electron-beam lithography uses electron beam.(d) ion beam lithography uses ion beam.
  20. 20. PhotolithographyPhotolithography is the process of transferring geometric shapes on a mask tothe surface of a silicon wafer. The steps involved in the photolithographicprocess are wafer cleaning; barrier layer formation; photoresist application; softbaking; mask alignment; exposure and development; and hard-baking.a) Wafer Cleaning, Barrier Formation and Photoresist ApplicationIn the first step, the wafers are chemically cleaned to remove particulate matteron the surface as well as any traces of organic, ionic, and metallic impurities.After cleaning, silicon dioxide, which serves as a barrier layer, is deposited onthe surface of the wafer. After the formation of the SiO2 layer, photoresist isapplied to the surface of the wafer. High-speed centrifugal whirling of siliconwafers is the standard method for applying photoresist coatings in ICmanufacturing. This technique, known as "Spin Coating," produces a thinuniform layer of photoresist on the wafer surface. Positive and Negative PhotoresistThere are two types of photoresist: positive and negative. For positive resists,the resist is exposed with UV light wherever the underlying material is to beremoved. In these resists, exposure to the UV light changes the chemicalstructure of the resist so that it becomes more soluble in the developer. Theexposed resist is then washed away by the developer solution, leaving windowsof the bare underlying material. In other words, "whatever shows, goes." Themask, therefore, contains an exact copy of the pattern which is to remain on thewafer.Negative resists behave in just the opposite manner. Exposure to the UV lightcauses the negative resist to become polymerized, and more difficult to
  21. 21. dissolve. Therefore, the negative resist remains on the surface wherever it isexposed, and the developer solution removes only the unexposed portions.Masks used for negative photoresists, therefore, contain the inverse (orphotographic "negative") of the pattern to be transferred. The figure belowshows the pattern differences generated from tuseopositive and negative resist.Negative resists were popular in the early history of integrated circuitprocessing, but positive resist gradually became more widely used since theyoffer better process controllability for small geometry features. Positive resistsare now the dominant type of resist used in VLSI fabrication processes. Figure-5b) Soft-BakingSoft-baking is the step during which almost all of the solvents are removed fromthe photoresist coating. Soft-baking plays a very critical role in photo-imaging.The photoresist coatings become photosensitive, or imageable, only aftersoftbaking. Oversoft-baking will degrade the photosensitivity of resists by eitherreducing the developer solubility or actually destroying a portion of thesensitizer. Undersoft-baking will prevent light from reaching the sensitizer.Positive resists are incompletely exposed if considerable solvent remains in thecoating. This undersoft-baked positive resists is then readily attacked by thedeveloper in both exposed and unexposed areas, causing less etching resistance.c) AlignmentIn order to make useful devices the patterns for different lithography steps thatbelong to a single structure must be aligned to one another. The first patterntransferred to a wafer usually includes a set of alignment marks, which are highprecision features that are used as the reference when positioning subsequentpatterns, to the first pattern (as shown in figure 4). Often alignment marks are
  22. 22. included in other patterns, as the original alignment marks may be obliterated asprocessing progresses. It is important for each alignment mark on the wafer tobe labeled so it may be identified, and for each pattern to specify the alignmentmark (and the location thereof) to which it should be aligned. By providing thelocation of the alignment mark it is easy for the operator to locate the correctfeature in a short time. Each pattern layer should have an alignment feature sothat it may be registered to the rest of the layers Figure-6d) Mask Alignment and ExposureOne of the most important steps in the photolithography process is maskalignment. A mask or "photomask" is a square glass plate with a patternedemulsion of metal film on one side. The mask is aligned with the wafer, so thatthe pattern can be transferred onto the wafer surface. Each mask after the firstone must be aligned to the previous pattern.
  23. 23. Once the mask has been accurately aligned with the pattern on the waferssurface, the photoresist is exposed through the pattern on the mask with a highintensity ultraviolet light. There are three primary exposure methods: contact,proximity, and projection. They are shown in the figure below.Contact PrintingIn contact printing, the resist-coated silicon wafer is brought into physicalcontact with the glass photomask. The wafer is held on a vacuum chuck, and the
  24. 24. whole assembly rises until the wafer and mask contact each other. Thephotoresist is exposed with UV light while the wafer is in contact position withthe mask. Because of the contact between the resist and mask, very highresolution is possible in contact printing (e.g. 1-micron features in 0.5 micronsof positive resist). The problem with contact printing is that debris, trappedbetween the resist and the mask, can damage the mask and cause defects in thepattern.Proximity PrintingThe proximity exposure method is similar to contact printing except that a smallgap, 10 to 25 microns wide, is maintained between the wafer and the maskduring exposure. This gap minimizes (but may not eliminate) mask damage.Approximately 2- to 4-micron resolution is possible with proximity printing.Projection PrintingProjection printing, avoids mask damage entirely. An image of the patterns onthe mask is projected onto the resist-coated wafer, which is many centimetersaway. In order to achieve high resolution, only a small portion of the mask isimaged. This small image field is scanned or stepped over the surface of thewafer. Projection printers that step the mask image over the wafer surface arecalled step-and-repeat systems. Step-and-repeat projection printers are capableof approximately 1-micron resolution.
  25. 25. e) Development:One of the last steps in the photolithographic process is development. Thefigure below shows response curves for negative and positive resist afterexposure and development.At low-exposure energies, the negative resist remains completely soluble in thedeveloper solution. As the exposure is increased above a threshold energy Et,more of the resist film remains after development. At exposures two or threetimes the threshold energy, very little of the resist film is dissolved. For positiveresists, the resist solubility in its developer is finite even at zero-exposureenergy. The solubility gradually increases until, at some threshold, it becomescompletely soluble. These curves are affected by all the resist processingvariables: initial resist thickness, prebake conditions, developer chemistry,developing time, and others.
  26. 26. f) Hard-BakingHard-baking is the final step in the photolithographic process. This step isnecessary in order to harden the photoresist and improve adhesion of thephotoresist to the wafer surface.g) EtchingIn etching, a liquid ("wet") or plasma ("dry") chemical agent removes theuppermost layer of the substrate in the areas that are not protected byphotoresist.In semiconductor fabrication, dry etching techniques are generally used, as theycan be made anisotropic, in order to avoid significant undercutting of thephotoresist pattern. This is essential when the width of the features to be definedis similar to or less than the thickness of the material being etched (i.e. when theaspect ratio approaches unity).Etching is a critically important process module, and every wafer undergoesmany etching steps before it is complete. For many etch steps, part of the waferis protected from the etchant by a "masking" material which resists etching. Insome cases, the masking material is a photoresist which has been patternedusing photolithography.
  27. 27. The two fundamental types of etchants are:- (1) liquid-phase ("wet") and (2) plasma-phase ("dry").Wet etchingThe first etching processes used liquid-phase ("wet") etchants. The wafer can beimmersed in a bath of etchant, which must be agitated to achieve good processcontrol. Wet etchants are usually isotropic, which is often indispensable formicroelectromechanical systems, where suspended structures must be"released" from the underlying layer. They also require the disposal of largeamounts of toxic waste.Plasma etchingModern VLSI processes avoid wet etching, and use plasma etching instead.Plasma etching can be isotropic, i.e., exhibiting a lateral undercut rate on apatterned surface approximately the same as its downward etch rate, or can beanisotropic, i.e, exhibiting a smaller lateral undercut rate than its downward etchrate. Such anisotropy is maximized in deep reactive ion etching.Plasma etching is a form of plasma processing used to fabricate integratedcircuits. It involves a high-speed stream of glow discharge (plasma) of anappropriate gas mixture being shot (in pulses) at a sample. It is based onphysical bombardment with ions or atoms. Plasma is used to energize a chemically inert projectile so that it moves athigh velocity when it strikes the substrate. Momentum is transferred during thecollision. Substrate atoms are dislodged if projectile energy exceeds bondingenergy. This process is very similar to ion implantation, but low-energy ions areused to avoid implantation damage. Argon is the most commonly used ionsource.
  29. 29. PhotoresistsPhotoresists are classified into two groups: positive resists and negative resists. A positive resist is a type of photoresist in which the portion of the photoresist that is exposed to light becomes soluble to the photoresist developer. The portion of the photoresist that is unexposed remains insoluble to the photoresist developer. A negative resist is a type of photoresist in which the portion of the photoresist that is exposed to light becomes insoluble to the photoresist developer. The unexposed portion of the photoresist is dissolved by the photoresist developer.Differences between tone types Characteristic Positive Negative Adhesion to Silicon Fair Excellent Relative Cost More Expensive Less Expensive Developer Base Aqueous Organic Minimum Feature 0.5 μm and below ± 2 μm Step Coverage Better LowerWet Chemical Resistance Fair Excellent
  30. 30. Lift offLift-off process in microstructuring technology is a method of creatingstructures (patterning) of a target material on the surface of a substrate (ex.wafer) using a sacrificial material. It is an additive technique as opposed tomore traditional subtracting technique like etching.An inverse pattern is first created in the sacrificial stencil layer (ex. photoresist),deposited on the surface of the substrate. This is done by etching openingsthrough the layer so that the target material can reach the surface of thesubstrate in those regions, where the final pattern is to be created. The targetmaterial is deposited over the whole area of the wafer, reaching the surface ofthe substrate in the etched regions and staying on the top of the sacrificial layerin the regions, where it was not previously etched. When the sacrificial layer iswashed away (photoresist in a solvent), the material on the top is lifted-off andwashed together with the sacrificial layer below.After the lift-off, the target material remains only in the regions where it had adirect contact with the substrate.
  31. 31. Etching The process of etching is to remove the semiconductor layer that is leftexposed by developing process. Control parameters for etching are time,uniformity, temperature and concentration of each species and these should betaken into account. Etchants should be used at particular temperature specifiedfor them. Care should taken ensure that only clean and dry wafer enter foretching. During etching complete removal of the development resist should betaken to ensure as any residue left on the semi-conducting layer may inhibitetching action. During etching, movement or rotation should be such that theyenhance the uniformity of phenomenon.wet etchingFor isotropic wet etching, a mixture of hydrofluoric acid, nitric acid, and aceticacid (HNA) is the most common etchant solvent for silicon. The concentrationsof each etchant determines the etch rate. Silicon dioxide or silicon nitride isusually used as a masking material against HNA. As the reaction takes place,the material is removed laterally at a rate similar to the speed of etchingdownward. This lateral and downward etching process takes places even withisotropic dry etching which is described in the dry etch section. Wet chemicaletching is generally isotropic even though a mask is present since the liquidetchant can penetrate underneath the mask (Figure 2b). If directionality is veryimportant for high-resolution pattern transfer, wet chemical etching is normallynot used.Dry etchingSynonyms: plasma etching, gas etching, physical dry etching, chemicaldry etching, physical-chemical etchingDefinition:In dry etching, plasmas or etchant gasses remove the substratematerial. The reaction that takes place can be done utilizing highkinetic energy of particle beams, chemical reaction or acombination of both.
  32. 32. Physical dry etching:Physical dry etching requires high energy kinetic energy (ion, electron, orphoton) beams to etch off the substrate atoms. When the high energy particlesknock out the atoms from the substrate surface, the material evaporates afterleaving the substrate. There is no chemical reaction taking place and thereforeonly the material that is unmasked will be removed. The physical reactiontaking place is illustrated in Figure 3.Chemical dry etching:Chemical dry etching (also called vapor phase etching) does not use liquidchemicals or etchants. This process involves a chemical reaction betweenetchant gases to attack the silicon surface.The chemical dry etching process is usually isotropic and exhibits highselectively. Anisotropic dry etching has the ability to etch with finer resolutionand higher aspect ratio than isotropicetching. Due to the directional nature of dry etching, undercutting can beavoided. shows a rendition of the reaction that takes place in chemical dryetching. Some of the ions that are used in chemical dry etching istetrafluoromethane (CH4), sulfur hexafluoride (SF6), nitrogen trifluoride (NF3),chlorine gas (Cl2), or fluorine (F2).[3]
  33. 33. Reactive Ion Etching:Reactive ion etching (RIE) uses both physical and chemical mechanisms toachieve high levels of resolution. The process is one of the most diverse andmost widely used processes in industry and research. Since the processcombines both physical and chemical interactions, the process is much faster.The high energy collision from the ionization helps to dissociate the etchantmolecules into more reactive species.In the RIE-process, cations are produced from reactive gases which areaccelerated with high energy to the substrate and chemically react with thesilicon. The typical RIE gasses for Si are CF4, SF6 and BCl2 + Cl2. As seen inFigure 5, both physical and chemical reaction is taking place. Figure 6 depictssome micro/nano structures with high aspect ration etched using RIE
  34. 34. CHAPTER-5Metallization 1) Ohmic contactsA metal-semiconductor junction results in an Ohmic contact (i.e. a contact withvoltage independent resistance) if the Schottky barrier height, B, is zero ornegative. In such case, the carriers are free to flow in or out of thesemiconductor so that there is a minimal resistance across the contact. For an n-type semiconductor, this means that the workfunction of the metal must be closeto or smaller than the electron affinity of the semiconductor. For a p-typesemiconductor, it requires that the workfunction of the metal must be close to orlarger than the sum of the electron affinity and the bandgap energy. Since theworkfunction of most metals is less than 5 V and a typical electron affinity isabout 4 V, it can be problematic to find a metal that provides an Ohmic contactto p-type semiconductors with a large bandgap such as GaN or SiC.
  35. 35. 2) Schottky ContactA Schottky barrier refers to a metal-semiconductor contact having a largebarrier height (i.e. and low doping concentration that is less than thedensity of states in the conduction band or valence band. The potential barrierbetween the metal and the semiconductor can be identified on an energy banddiagram. To construct such a diagram we first consider the energy band diagramof the metal and the semiconductor, and align them using the same vacuumlevel as shown in Fig. 3.2 (a). As the metal and semiconductor are broughttogether, the Fermi energies of the two materials must be equal at thermalequilibrium Fig. 3.2 (b).The barrier height is defined as the potential difference between the Fermienergy of the metal and the band edge where the majority carrier reside.From Fig. 3.2 one finds that for n-type semiconductors the barrier height isobtained from
  36. 36. Techniques of metallizationPhysical vapor depositionPhysical vapor deposition (PVD) is a variety of vacuum deposition and is ageneral term used to describe any of a variety of methods to deposit thinfilms by the condensation of a vaporized form of the material onto varioussurfaces (e.g., onto semiconductor wafers). The coating method involves purelyphysical processes such as high temperature vacuum evaporation or plasmasputter bombardment rather than involving a chemical reaction at the surface tobe coated as inchemical vapor deposition. The term physical vapor depositionappears originally in the 1966 bookVapor Deposition by CF Powell, JH Oxleyand JM Blocher Jr, but Michael Faraday was using PVD to deposit coatings asfar back as 1838.Variants of PVD include, in order of increasing novelty: Cathodic Arc Deposition: In which a high power arc discharged at the target material blasts away some into highly ionized vapor. Electron beam physical vapor deposition: In which the material to be deposited is heated to a high vapor pressure by electron bombardment in "high" vacuum. Evaporative deposition: In which the material to be deposited is heated to a high vapor pressure by electrically resistive heating in "low" vacuum. Pulsed laser deposition: In which a high power laser ablates material from the target into a vapor. Sputter deposition: In which a glow plasma discharge (usually localized around the "target" by a magnet) bombards the material sputtering some away as a vapor. Here is an animation of a generic PVD sputter tool: PVD AnimationPVD is used in the manufacture of items including semiconductordevices, aluminized PET film for balloons and snack bags, and coated cuttingtools for metalworking. Besides PVD tools for fabrication special smaller toolsmainly for scientific purposes have been developed. They mainly serve thepurpose of extreme thin films like atomic layers and are used mostly for smallsubstrates. A good example are mini e-beam evaporators which can depositmonolayers of virtually all materials with melting points up to 3500°C.
  37. 37. sputteringSputter deposition is a physical vapor deposition process for depositingthin films, sputtering means ejecting material from a target and depositing it ona substrate such as a silicon wafer. The target is the source material. Substrates are placed in a vacuum chamberand are pumped down to a prescribed process pressure. Sputtering starts when anegative charge is applied to the target material causing a plasma or glowdischarge. Positive charged gas ions generated in the plasma region areattracted to the negatively biased target plate at a very high speed. This collisioncreates a momentum transfer and ejects atomic size particles form the target.These particles are deposited as a thin film into the surface of the substrates.Sputtering is extensively used in the semiconductor industry to deposit thinfilms of various materials in integrated circuits processing. Thin antireflection coatings on glass, which are useful for optical applications are alsodeposited by sputtering. Because of the low substrate temperatures used,sputtering is an ideal method to deposit contact metals for thin- film transistors.This technique is also used to fabricate thin film sensors, photovoltaic thin films(solar cells), metal cantilevers and interconnects etc.sputtering can be done either in DC or RF modes. DCsputtering is done with conducting materials. If the target is a non conductingmaterial the positive charge will build up on the material and it will stopsputtering. RF sputtering can be done both conducting and non conductingmaterials. Here, magnets are used to increase the percentage of electrons thattake part in ionization of events and thereby increase the probability of electronsstriking the Argon atoms, increase the length of the electron path, and henceincrease the ionization efficiency significantly.
  38. 38. sputtering can be done in either DC or RF modesDC sputtering: DC sputtering is done with conducting materials. If target is non-conducting material, the positive charge will built up on target material and stops sputteringRF sputtering: Both conducting and non-conducting materials can be sputtered. Higher sputter rate at lower pressure.Advantages of vacuum deposition: Reducing the particle density so that the mean free path for collision is long. Reducing the contaminants Low pressure plasma environment
  39. 39. Comparision of Thermal Evaporation and Sputtering: Evaporation Sputtering Low energy atoms High energy atoms High vacuum path Low vacuum path Few collision Many collision Larger grain size Smaller grain size Poorer adhesion Better adhesion
  40. 40. CONCLUSIONThe industrial training at DEFENCE RESEARCH AND DEVELOPMENTORGANISATION (DRDO), Delhi has given me an exposure to the activitiesat a large public sector – undertaking unit . This being a large organization dealswith wide spectrum of technologies . The exposure on LITHOGRAPHY hasgiven me great confidence and knowledge.
  41. 41. BIBLIOGRAPHYBooks Referred a) Vlsi Technology By S.M.SZE b) Vlsi Fabrication Principles by Ralph WilliamsWeb Section a) www.google.com b) www.wikipedia.com c) www.pdf.com d) http://www.ece.gatech.edu/research/labs/vc/theory/PosNegRes.html e) http://dspace.library.iitb.ac.in