1. SYSTEM DESIGN
• ANALOG DATA IS DIGITIZED FOR TRANSMISSION, STORAGE,
PROCESSNG AND DISPLAY.
• DATA SHOULD BE DIGITIZED RAPIDLY, FREQUENTLY,
ACCURATELY, COMPLETELY AND CHEAPLY AS REQUIRED.
• FOR ACCOMODATING THE INPUT VOLTAGE TO THE
SPECIFIED CONVERSION RELATIONSHIP, SOME FORM OF
SCALING AND OFFSETTING (SIGNAL CONDITIONING) IS
NECESSARY.
• ONE NEEDS AMPLIFIERS AND ATTENUATORS.

2. SYSTEM DESIGN
• MUX IS REQUIRED FOR HANDLING MORE THAN ONE SOURCE
OF DATA.
• TO INCREASE THE RATE AT WHICH THE INFO MAY BE
ACCURATELY CONVERTED, A S/H IS DESIRABLE.
• A LOGARITHMIC AMPLIFIER IS USEFUL FOR COMPRESSING
AN EXTRA WIDE ANALOG DYNAMIC RANGE.
• THE PROPERTIES OF DATA ACQUISITION SYSTEM DEPENDS
UPON THE ANALOG DATA AND ITS PROCESSING.

3. SYSTEM DESIGN
• THOUGH THE ADVENT OF SEMICONDUCTOR DEVICES HAVE
LED TO SMALLER, QUITE, COOL AND LOW-COST SYSTEMS AS
THESE ARE LOW CURRENT DRAIN COMPONENTS BUT THE
BASIC DESIGN PROBLEMS LIKE NOISE, EMI, GROUND LOOPS,
POWER LINE PICK UP AND TRANSIENTS USED IN SIGNAL
LINES FROM THE MACHINARY ARE TO BE CONFRONTED.
• ONE HAS TO THINK ABOUT THE ENVIRONMENT AS USUALLY
THE ANALOG DATA IS GENERATED IN HOT, NOISY
ENVIRONMENT, PROCESSING IS DONE IN A QUIET CONTROL
ROOM AND THE RESULTS ARE TRANSMITTED THROUGH A
WORLD FULL OF INTERFERENCES.

4. SYSTEM DESIGN
• ENVIRONMENT MAY GIVE RISE TO CONSIDERATIONS SUCH AS:
 ANALOG VS DIGITAL SIGNAL TRANSMISSION
 SIGNAL ACCURACY VS WAVEFORM RECOVERY
 ISOLATION VS DIRECT WIRING
 SIMPLE VS COMPLEX ARCHITECTURE
 INTEGRATED VS DISTRIBUTED APPROACHES
 LOCAL VS REMOTE PROCESSING
 CHOICE OF POWER SUPPLY AND OTHER HW

5. SYSTEM DESIGN
• ACTIVE HOSTILE ENVIRONMENTS ARE:
 PHYSICALLY: TEMPERATURE, PRESSURE, ACCELERATION,
HUMIDITY, RADIATION, ETC.
 CHEMICALLY: SALT SPRAY, BIOLOGICAL FLUIDS, DIRT,
CHEMICALLY ACTIVE FLUID AND GAS.
 ELECTRICALLY: HIGH VOLTAGES AND MAGNETIC FIELDS, DC,
AC TRANSIENT INTERFERENCE OVER THE WHOLE
SPECTRUM.

6. SYSTEM DESIGN
• SYSTEMS THAT WORK IN SUCH ENVIRONMENTS REQUIRE
ELECTRONIC DEVICES CAPABLE OF WIDE TEMPERATURE
RANGE OPERATION, EXCELLENT SHIELDING, CONSIDERABLE
DESIGN EFFORT AIMED AT ELIMINATING COMMON MODE
ERRORS, GOOD TRANSMISSION SYSTEM, REDUNDANT PATH
FOR CRITICAL MEASUREMENT, ETC.
• MEASUREMENT IN THE LAB WITH NARROWER
TEMPERATURE RANGES AND ALMOST NO ELECTRICAL
INTEFERENCE IS EASIER AND ITS COMMUNICATION IS ALSO
EASIER BUT HIGHER ACCURACY REQUIRES MORE SENSITIVE
DEVICES PLUS EFFORTS TO MAINTAIN THE APPROPRIATE S/
N RATIO.

7. SYSTEM DESIGN
• BESIDES ENVIRONMENT, WHICH ADDS MANY PRACTICAL PROBLEMS, THE
CHOICE OF CONFIGURATION AND CIRCUIT BUILDING BLOCKS IN ANY DAS
DEPENDS UPON:
o RESOLUTION AND ACCURACY
o NO. OF CHANNELS TO BE MONITORED
o SAMPLING RATE PER CHANNEL
o THROUGHPUT RATE
o SIGNAL CONDITIONING REQUIREMENTS
o INTENDED DISPOSITION OF CONVERTED DATA AND
o THE COST FUNCTION

8. SYSTEM DESIGN
• THE OBJECTIVE ALWAYS IS TO OBTAIN THE LOWEST COST
CIRCUIT CONFIGURATION TO OBTAIN THE DESIRED OVERALL
PERFORMANCE.
• TYPICAL CONFIGURATIONS MAY BE:
 1-CHANNEL: DIRECT CONVERSION; S/H & CONVERSION;
PREAMPLIFICATION AND SIGNAL CONDITIONING.
 n-CHANNEL: MULTIPLEXING THE OUTPUT OF SINGLE
CHANNEL CONVERTERS, MULTIPLEXING CONVERTER
INPUTS, MULTIPLEXING THE INPUTS OF S/H, MULTIPLEXING
THE OUTPUTS OF S/H.

9. SYSTEM DESIGN
• FOR SIGNAL CONDITIONING, ONE USES:
 IN RATIOMETRIC CONVERSION: RANGE BIASING; AUTOMATIC
GAIN SWITCHING; LOGARITHMIC COMPRESSION;
LOGARITHMIC CONVERSION; DIGITAL CORRECTION OF
ANALOG ERRORS
 FOR NOISE REDUCTION: FILTERING, INTEGRATING TYPE
CONVERTERS, DIGITAL PROCESSING.
 WHILE MAKING TRADE-OFFS, ONE HAS TO ALWAYS KEEP IN
MIND – HOW MUCH ERROR CAN BE TOLERATED AND THE
SYSTEM RESPONSE TIME – ACCURACY AND TIMELINESS OF
DATA.

10. SYSTEM DESIGN
• SINGLE CHANNEL CONVERSION SUBSYSTEMS:
 SIMPLEST IS THE FREE RUNNING A/D CONVERTER WHERE
THE CONV RATE IS DETERMINED BY THE TIME FOR
COMPLETE CONVERSION.
 FOR DC AND LOW FREQ SIGNALS, THE CONV IS DUAL SLOPE
TYPE AS IT IS INHERENTLY A LPF, CAPABLE OF AVERAGING
OUT HF NOISE AND NULLING FREQS HARMONICALLY
RELATED TO ITS INTEGRATING PERIOD.
 FOR THIS REASON, THE INTEGRATION PERIOD IS USUALLY
MADE EQUAL TO THE PERIOD OF THE LINE FREQ. SINCE THE
MAJOR PORTION OF SYSTEM INTERFERENCE USUALLY
OCCURS AT THAT FREQ AND ITS HARMONICS.

11. SYSTEM DESIGN
• THE ACTUAL VALUE OF THE INPUT THAT IS CONVERTED BY
AN INTEGRATING TYPE CONVERTER IS REPRESENTED BY
THE AVERAGE OVER THE SIGNAL INTEGRATION INTERVAL.
SINCE THAT INTERVAL IS A FRACTION OF THE TOTAL TIME
REQUIRED (~1/3) FOR THE CONVERSION CYCLE, ONE CAN
SAY THAT THE DIGITAL OUTPUT REPRESENTS THE MOST
PROBABLE VALUE DURING A SIGNIFICANT PORTION OF THE
CONVERSION PERIOD.
• THAT IS THE DUAL SLOPE INTEGRATING A/D CONV SPENDS
ABOUT 1/3 OF ITS SAMPLING PERIOD IN PERFORMING THE
INTEGRATION AND THE REMAINDER TIME IS SPENT IN
COUNTING THE AV VALUE OVER THE INTEGRATION PERIOD
AS A DIGITAL NUMBER, AND RESTTING TO INITIAL
CONDITIONS FOR THE NEXT SAMPLE.

12. SYSTEM DESIGN
• THOUGH SLOW, IT IS USEFUL FOR TEMP CONVERSION, BATTERY
DISCHARGE, SLOWLY VARYING VOLTAGES PARTICULARLY IN THE
PRESENCE OF THE NOISE.
• THE MOST POPULAR CONVERTER IS SUCCESSIVE APPROX A/D CONV AS IT
HAS HIGH RESOLUTION, HIGH SPEED (1 MICROSEC FOR 12 BIT CONV) AND
REASONABLE COST.
• ITS PROBLEM IS THAT AT HIGHER RATES OF CHANGE, IT GENERATES
LINEARITY ERROR BECAUSE IT CAN NOT TOLERATE CHANGE DURING THE
WEIGHING PROCESS. THE CONVERTED VALUE WILL BE AT SOME VALUE
BETWEEN THE EXTREME VALUES OCCURING DURING CONVERSION AND
THE TIME UNCERTAINTY APPROACHES THE MAGNITUDE OF THE
CONVERSION INTERVAL.
• EVEN FOR A SLOWLY VARYING SIGNAL, NOISE RATES OF CHANGE THAT
ARE EXCESSIVELY LARGE WILL CAUSE ERRONEOUS READINGS THAT CAN
NOT BE AVERAGED, BY EITHER ANALOG OR DIGITAL MEANS.

13. SYSTEM DESIGN
• USE OF SAMPLE HOLD:
 A CONVERTER CAN BE MADE TOMOPERATE AT
CONSIDERABLY GREATER ACCURACIES AT HIGH SPEED
WITH PRECISE TIMING OF SAMPLES, IRRESPECTIVE OF THE
TIME REQUIRED TO COMPLETE A CONVERSION BY
INTRODUCING A S/H BETWEEN THE INPUT SIGNAL AND THE
CONVERTER’S INPUT.
 BETWEEN CONVERSIONS, THE S/H DEVICE MAY ACQUIRE
AND TRACK THE INPUT SIGNAL.
 JUST BEFORE A CONVERSION IS TO TAKE PLACE, IT IS
SWITCHED TO HOLD AND REMAINS IN THAT STATE
THROUGHOUT THE CONVERSION.

14. SYSTEM DESIGN
• IF THE S/H RESPONDS INSTANTANEOUSLY AND
ACCURATELY, THE CONV CAN ACCURATELY CONVERT
SIGNALS HAVING RATES OF CHANGE OF ANY MAGNITUDE,
AT SAMPLING RATES UP TO THE ADC’S MAXIMUM CONV
RATE.
• BUT PRACTICAL PROBLEMS ARE TIME RELATED ERRORS
SUCH AS ACQUISITION TIME, TRACKING DELAY AND
APERTURE TIME. TYPICAL VALUES ARE 5 MICROSEC
ACQUISITION TIME TO 0.01%, 50 ns TRACKING DELAY AND 25
ns APERTURE TIME WITH 0.5 ns UNCERTAINTY.
• APERTURE UNCERTAINTY CAN NOT BE TOTALLY REMOVED
AND HENCE THE TIME RELATED ERROR WILL BE THERE.

15. SYSTEM DESIGN
• IN ORDER TO AVOID ERRORS DUE TO AN INSUFFICIENT NUMBER OF
SAMPLES, THE SAMPLING THEOREM TELLS US THAT REGULARLY
SPACED SAMPLES MUST OCCUR AT LEAST AT THE NYQUIST RATE
ie., TWICE THE FREQ OF THE HIGHEST FREQ SIGNAL OR NOISE
COMPONENT.
• THAT IS, EITHER A SUFFICIENTLY HIGH SAMPLING RATE MUST BE
EMPLOYED OR ELSE ALL COMPONENTS OF SIGNALS AND NOISE AT
FREQS EQUAL TO OR GREATER THAN THE NYQUIST FREQ ie., ONE-
HALF THE SAMPLING RATE, MUST BE FILTERED OUT BEFORE
SAMPLING.
• SINCE PRACTICAL FILTERS REQUIRE A COMPROMISE BETWEEN
ATTENUATION IN THE PASS BAND AND TRANSMISSION IN THE STOP
BAND, THE SAMPLING RATE IS OFTEN 3 OR MORE TIMES THE
FILTER CUT-OFF FREQUENCY.

16. SYSTEM DESIGN
• IF ANALOG SIGNALS AT HIGHER FREQ ARE PRESENT, THE
SAMPLING PROCESS WILL PRODUCE THE SUM AND DIFFERENCE
FREQS WITH THE SAMPLING FREQ AND ITS HARMONICS
• THE DIFFERENCE FREQUENCIES WILL PRODUCE SPURIOUS LOW
FREQ SIGNALS OR ALIASES IN THE SIGNAL PASS BAND THAT CAN
NOT BE DISTINGUISHED FROM THE SIGNAL.
• SINCE S/H USUALLY OPERATES AT UNITY GAIN, SCALING OR
PREAMPLIFICATION, SHOULD USUALLY OCCUR BEFORE THE
SIGNAL IS APPLIED TO THE SAMPLE-HOLD.

17. SYSTEM DESIGN
• PREAMPLIFICATION:
o USUALLY, CONVERTERS ARE SINGLE ENDED W.R.T. POWER
COMMON ( SOME ARE DIFFERENTIAL AND HAVE EVEN ISOLATED,
FLOATING INPUTS) AND HAVE NORMALISED INPUT RANGES OF 5 OR
10 V, SINGLE ENDED OR BIPOLAR.
o THE SIGNAL INPUT TO A/D CONV IS SCALED UP OR DOWN TO THE
STANDARD CONVERTER INPUT LEVEL, TO MAKE FULLEST POSSIBLE
USE OF THE CONVERTER’S AVAILABLE RESOLUTION.
o THE PREAMPLIFIER SHOULD HAVE LOW DYNAMIC OUTPUT
IMPEDANCE, BECAUSE THE INPUTS OF SME TYPES OF A/D
CONVERTERS MAY HAVE LARGE CURRENT PULSES, WHICH WILL
LOAD THE PREAMPLIFIER’S OUTPUT AND CAN CAUSE ERRORS.

18. SYSTEM DESIGN
• SOME A/D CONVERTERS HAVE ON-CHIP PREAMP (mV – V). THE ON-
CHIP PREAMP ALSO BUFFERS THE INPUT SOURCE FROM THE
CONVERSION PROCESS.
• IF THE SIGNALS ARE OF REASONABLE AMPLITUDE, AND ALREADY
EXIST WITHIN A SYSTEM REFERENCED TO A GOOD QUALITY
COMMON GROUND, THE SCALING MAY BE SIMPLY DONE WITH
OP.AMPS. IN A SINGLE-ENDED OR DIFFERENTIAL CONFIGURATION.
• IF THE SIGNALS ARE FROM OUTSIDE THE SYSTEM OR ARE QUITE
SMALL OR HAVE AN APPRECIABLE COMMON MODE COMPONENT,
THEN ONE SHOULD USE A DIFFERENTIAL INSTRUMENTATION
AMPLIFIER WITH CHARACTERISTICS THAT DEPEND ON THE GAIN
REQUIRED, THE SIGNAL LEVEL, THE NEEDED CMR, BW, IMPEDANCE
LEVELS AND COST TRADE-OFFS.

19. SYSTEM DESIGN
• IF THE INPUT SIGNAL IS TO BE COMPLETELY ISOLATED
FROM THE SYSTEM THEN AN ISOLATION AMPLIFIER IS
REQUIRED TO BREAK ALL CONDUCTIVE SIGNAL PATHS.
• IT IS REQUIRED IN ENVIRONMENTS WHERE COMMON MODE
SPIKES ARE ENCOUNTERED OR IN APPLICATIONS WHERE
THE SIGNAL SOURCE IS AT A HIGH OFF-GROUND POTENTIAL.

20. SYSTEM DESIGN
• SIGNAL CONDITIONING:
o CAN BE DONE BY ANALOG/DIGITAL TECHNIQUES.
o eg., LINEARIZATION OF DATA FROM THERMOCOUPLES/
BRIDGES CAN BE PERFORMED BY ANALOG TECHNIQUES,
USING EITHER PIECEWISE LINEAR APPROX. (BIASED DIODE
CIRCUIT) OR SMOOTH SERIES APPROX.(ANALOG
MULTIPLIERS).
o IT CAN ALSO BE DONE DIGITALLY, AFTER CONVERSION, BY
PERFORMING THE NECESSARY CALCULATIONS WITH A
MICROPROCESSOR OR BY STORING THE INVERSE OR
COMPLIMENTARY FN IN A ROM LOOK UP TABLE.

21. SYSTEM DESIGN
• ANALOG DIFFERENTIATION CAN BE USED TO MEASURE
CONTINUOUSLY THE RATE AT WHICH THE INPUT VARIES.
• INTEGRATION COULD BE USED TO OBTAIN TOTAL DOSAGE FROM A
RATE OF FLOW.
• AN OP.AMP. , CONNECTED AS A SIMPLE ALL-PASS FILTER, CAN BE
USED TO PROVIDE AN ARBITRARY PHASE SHIFT.
• SUMS AND DIFFERENCES COULD BE USED TO REDUCE THE
NUMBER OF DATA INPUTS.
• ANALOG MULTIPLIERS CAN BE USED TO COMPUTE POWER BY
SQUARING VOLTAGE OR CURRENT SIGNALS OR MULTIPLYING
THEM TOGETHER.

22. SYSTEM DESIGN
• RMS TO D CONVERTERS COMPUTE RMS DIRECTLY.
• ANALOG DIVIDERS ARE USED FOR COMPUTING RATIOS,
LOGS OF RATIOS OR SQ.ROOTS.
• COMPARATORS ARE USED TO MAKE DECISIONS BASED ON
ANALOG LEVELS (FOR EXAMPLE TO CONVERT ONLY WHEN
THE INPUT EXCEEDS A THRESHOLD OR IS WITHIN A
WINDOW)
• LOG CIRCUITS ARE USED FOR RANGE COMPRESSION TO
PERMIT THE CONVERSION OF SIGNALS HAVING WIDE
DYNAMIC RANGES. CONVERTERS HAVING LESS
RESOLUTION MAY BE EMPLOYED.

23. SYSTEM DESIGN
• ACTIVE FILTERS ARE USED TO MINIMIZE THE EFFECT OF NOISE,
CARRIER FREQS AND UNWANTED HF COMPS OF THE INPUT SIGNAL.
• ANALOG FILTERS CAN BE EITHER FIXED OR DIGITALLY
PROGRAMMABLE, USING D/A CONVERTERS.
• BASIC POINT IS THAT IN ANY SYSTEM DESIGN, ALL DATA
PROCESSING NEED NOT BE DIGITAL.
• ANALOG CIRCUITS CAN PERFORM LOCAL OR REMOTE PROCESSING
OR DATA REDUCTION RELIABLY, EFFECTIVELY AND ECONOMICALLY
AND IS AN ALTERNATE WAY OF REDUCING SW COMPLEXITY, NOISE,
BOARD SPACE AND COST.

24. SYSTEM DESIGN
• n-CHANNEL SYSTEM:
 HERE, THE ELEMENTS OF THE SYSTEM MAY BE SHARED BY 2
OR MORE INPUT SOURCES. THIS SHARING MAY OCCUR IN
SEVERAL WAYS, DEPENDING ON THE DESIRED PROPERTIES
OF THE MULTIPLEXED SYSTEM.
 LARGE SYSTEMS MAY COMBINE SEVERAL TYPES OF
MULTIPLEXING OR MAY HAVE CASCADED TIERS OF THE
SAME TYPE.
 CONVENTIONAL METTHOD OF DIGITIZING DATA FROM MANY
ANALOG SOURCES IS TO INTRODUCE THE TIME SHARING
PROCESS AT THE ANALOG PORTION OF THE SYSTEM BY
MULTIPLEXING THE INPUT OF A SINGLE A/D CONV AMONG
THE VARIOUS ANALOG SOURCES IN SEQUENCE.

25. SYSTEM DESIGN
• WITH THE DECLINE IN THE COST OF THE DEVICE ONE CAN NOW
AFFORD THE PARALLEL CONVERSION PROCESS.
• FOR A MODEST DATA RATE, WITH MORE CHANNELS AND FEWER
CONVERSIONS PER CHANNEL, IT MAY BE POSSIBLE TO ELIMINATE
THE S/H DEVICE.
• FEWER CONVERSIONS ALSO MEAN THAT SLOWER CONVERTERS
CAN BE AFFORDED.
• THE BUS STRUCTURES USED BY THE PROCESSOR ENCOURAGE
THE USE OF DIGITAL MUX, WITH ALL DEVICES CONNECTED TO THE
BUS VIA TRI-STATE SWITCHES ENABLED SELECTIVELY BY CS LOGIC
SIGNALS FROM DECODERS AND R/W CONTROL SIGNALS.(WRITE TO
INITIATE CONVERSIONS AND READ TO OBTAIN RESULTS)

26. SYSTEM DESIGN
• DIGITIZING THE ANALOG SIGNAL AT THE SOURCE AND
TRANSMITTING SERIAL DATA HAS THE ADVANTAGE OF
CONSIDERABLE IMMUNITY TO LINE FREQ PICK-UP AND GROUND
LOOP INTERFERENCE.
• THE DIGITAL SIGNALS CAN BE COUPLED OPTICALLY OR EVEN
TRANSMITTED VIA FIBRE OPTIC LINKS FOR COMPLETE ELECTRICAL
ISOLATION AND TOTAL INDIFFERENCE TO ELECTRICAL
INTERFERENCE.
• ANOTHER WAY IS TO USE V-F CONV FOR TRANSMITTING DATA
GENERATED BY SLOWLY VARYING SIGNALS WITH DYNAMIC
RANGES OF UPTO 106 AND REQUIRING ACCURACIES TO WITHIN
0.01%. THE OUTPUTS ARE TTL PULSE TRAINS WHICH MAY BE
EASILY ISOLATED OPTICALLY. THE OUTPUT OF EACH V-F IN TURN IS
COUNTED AND READ. THE COMPUTER CONTROLS THE MUX AND
ACTS AS THE TIME BASE FOR THE COUNTER.

27. SYSTEM DESIGN
• SO, LOGIC DECISION CIRCUITS OR LOCAL
MICROPROCESSOR CAN DECIDE WHEN AND WHICH DATA IS
TO BE FED TO THE HOST COMPUTER (MADE POSSIBLE BY
DIGITAL MULTIPLEXING).
• THE COMPUTER CAN’T MAKE DECISIONS ABOUT THE DATA
SENT THROUGH ANALOG MUX UNTIL THE DATA HAS BEEN
RECEIVED ie., REDUNDANT INFORMATION IS SORTED AT THE
TRANSMITTING END ITSELF- BECOMES VERY USEFUL IN
CASE OF CROWDED CHANNELS.

28. SYSTEM DESIGN
• LINEAR TIME INVARIANT SYSTEM:
 A SYSTEM IS SAID TO BE LINEAR IF AND ONLY IF THE
SUPERPOSITION THEOREM IS SATISFIED WHICH STATES THAT THE
OUTPUT RESPONSE OF A LTI SYSTEM TO A NUMBER OF
SIMULTANEOUSLY APPLIED INPUTS IS EQUAL TO THE SUMMATION
OF THE SYSTEM RESPONSES WHEN EACH INPUT IS APPLIED
INDIVIDUALLY.
 A SYSTEM IS SAID TO BE TIME INVARIANT WHEN THE
COEFFICIENTS OF THE DIFFERENTIAL OR DIFFERENCE EQUATION
RELATING TO THE SYSTEM’S OUTPUT TO ITS INPUT DO NOT
DEPEND UPON TIME.
 IN GENERAL, IF A SPECIFIED INPUT IS APPLIED TO A GIVEN SYSTEM
AT ANY TIME Ti OR Tj, AND IF THE OUTPUT RESPONSES TO EACH
APPLICATION OF THE INPUT ARE THE SAME, THE SYSTEM IS SAID
TO BE TIME-INVARIANT.

29. SYSTEM DESIGN
• SHANNON’S SAMPLING THEOREM:
 IT STATES THAT “ A FN OF TIME e(t) WHICH CONTAINS NO
FREQ COMPS GREATER THAN ωc RAD/S CAN BE
RECONSTRUCTED BY THE VALUES OF e(t) AT ANY SET OF
SAMPLING POINTS THAT ARE SPACED APART BY T < Π/ ωc
SEC.”
 THIS THEOREM GIVES THE MAXIMUM VALUE OF T
PERMISSIBLE IN ORDER TO BE ABLE TO RECONSTRUCT THE
ORIGINAL SAMPLED SIGNAL.
 IN OTHER WORDS, ONE CAN SAY THAT THERE EXISTS AN
UPPER BAND THAT SPECIFIES THAT A SUFFICIENT NO OF
IMPULSE SAMPLES BE TAKEN TO COMPLETELY
CHARACTERISE e(t).

30. SYSTEM DESIGN
• SO, THE FOLLOWING SAMPLING FREQ CRITERION IS USED:
ωs > 2.ωc OTHERWISE OVERLAPING TAKES PLACE AND
ALIASING OCCURS.
• THE SELECTION OF THE SAMPLING RATE MUST ALSO
CONSIDER NOISE, DATA ACQUISITION, SYSTEM RESONANT
FREQUENCIES AND DESIGN TECHNIQUE. THESE FACTORS
USUALLY DICTATE A NOMINAL VALUE OF SAMPLING FREQ AT
LEAST 8 TIMES GREATER THAN ωc, DEPENDING UPON THE
SPECIFIC VALUE OF DIFFERENT PARAMETERS.
• THE SAMPLING SCHEDULE CAN BE UNIFORM RATE, MULTI-
RATE, SKIP SAMPLING, VARIABLE SAMPLING OR RANDOM
SAMPLING. MOSTLY, UNIFORM SAMPLING SCHEDULE IS
PREFERRED.

31. SYSTEM DESIGN
• BECAUSE OF THE FINITE WORD LENGTH, DECREASING T
INCREASES THE REQUIRED COMPUTATION TIME AS WELL AS
THE ROUND-OFF AND TRUNCATON ERRORS. SO, A TRADE-
OFF IS REQUIRED AS INCREASING T GIVES RISE TO ALIASING
OR FREQ FOLDING PROBLEMS.
• AS THE SAMPLED SIGNAL e*(t) CONTAINS THE FREQ COMPS
OF CONTINUOUS SIGNAL e(t) AND THE HIGH FREQ COMPS
RESULTING FROM THE SAMPLING PROCESS, IN ADITION TO
LPF ONE NEEDS THE SAMPLE/HOLD DEVICE WHICH
EFFECTIVELY CONVERTS THE IMPULSE SIGNAL e*(t) INTO A
CONTINUOUS SIGNAL m(t) EITHER BY MEANS OF
INTERPOLATION OR EXTRAPOLATION OF THE INPUT
IMPULSES WHOSE FORM APPROXIMATES THE FORM OF THE
INPUT SIGNAL e(t).

32. SYSTEM DESIGN
• THE IDEAL FILTER CHARACTERISTICS MAY BE APPROACHED BY
DECREASING THE SAMPLING TIME T
• DECREASING T INCREASES THE BW BUT DECREASES THE MAGNITUDE OF
THE FREQ SPECTRUM. ALTHOUGH THE PRIMARY COMPONENT
APPROACHES THE IDEAL FILTER CHARACTERISTICS THE BW INCREASES.
• THIS INCREASED BW DEGRADES THE ZOH UNIT’S CAPABILITY TO MINIMIZE
THE UNWANTED FREQS.
• THE TERM ZERO ORDER REFERS TO THE CAPABILITY OF THE DEVICE TO
PASS WITHOUT DISTORTION A CONSTANT ie., A ZERO ORDER POLYNOMIAL.
• THEN, BY DEFINITION, A FIRST ORDER HOLD DEVICE PASSES WITHOUT
DISTORTION A FIRST ORDER POLYNOMIAL SIGNAL. EFFECTIVELY, A FIRST
ORDER HOLD IS A SIGNAL EXTRAPOLATOR USING THE FIRST DIFFERENCE
EQUATION.

33. SYSTEM DESIGN
• THE nth ORDER HOLD DEVICE THEN PASSES WITHOUT
DISTORTION nth ORDER POLYNOMIAL. GENERALLY, ONLY
ZERO ORDER HOLD DEVICE IS IMPLEMENTED THROUGH
HW, HIGHER ORDER HOLD ALGOS ARE IMPLEMENTED IN
SW.
• THE PERFORMANCE OF A CONTROL SYSTEM BASED UPON
A STEP INPUT, FALLS INTO THE FOLLOWING CATEGORIES:
5. A GIVEN SYSTEM IS STABLE AND ITS TRANSIENT
RESPONSE IS SATISFACTORY, BUT ITS STEADY STATE
ERROR IS TOO LARGE. SO THE GAIN MUST BE INCREASED
TO DECREASE THE STEADY STATE ERROR WITHOUT
APPRECIABLY REDUCING THE SYSTEM STABILITY.

34. SYSTEM DESIGN
1. A GIVEN SYSTEM IS STABLE BUT ITS TRANSIENT
RESPONSE IS UNSATISFACTORY.
3. A GIVEN SYSTEM IS STABLE BUT BOTH ITS TRANSIENT
RESPONSE AND STEADY STATE RESPONSE ARE
UNSATISFACTORY.
5. A GIVEN SYSTEM IS UNSTABLE FOR ALL VALUES OF GAIN.
• IN ANY OF THE ABOVE CASES, ADDITIONAL COMPS ARE
REQUIRED TO ACHIEVE THE DESIRED SYSTEM
PERFORMANCE. IT IS REFERRED TO AS COMPENSATOR
OR CONTROLLER – LAG, LEAD OR LAG-LEAD

35. SYSTEM DESIGN
• A LAG NETWORK IS A LPF USED FOR SYSTEM IN CATEGORY
1.
• IT IS KNOWN AS A LAG NETWORK SINCE FOR A SINUSOIDAL
INPUT THE OUTPUT PHASE ALWAYS LAGS RELATIVE TO THE
INPUT PHASE.

36. SYSTEM DESIGN
• A LEAD NETWORK IS A HPF, USED FOR SYSTEMS WHOSE
PERFORMANCE FALLS INTO CATEGORY 2 OR 4.

37. SYSTEM DESIGN
• THE IMPROVEMENT ACHIEVED WITH THE HELP OF ABOVE
NETWORKS CAN BE OBTAINED WITH A SINGLE CIRCUIT KNOWN AS
LAG-LEAD NETWORK, USED FOR SYSTEMS IN CATEGORY 3.
• THIS COMPENSATOR IS USED GENERALLY IN THE PROCESS
CONTROL INDUSTRY AND IS KNOWN AS PID CONTROLLER. IT IS A
THREE-TERM CONTROL.
• ITS TRANSFER FN IS Gc(s) = Kp + Kd.s + Ki/s
• IT IS GENERALLY USED BECAUSE IT REQUIRES VERY LITTLE
KNOWLEDGE OF PLANT DYNAMICS AND THE METHOD OF
DETERMINING THE CONTROLLER PARAMETERS ARE WELL KNOWN.

38. SYSTEM DESIGN
• CONTROLLER:
M(s) C(s)
R(s) E(s)
Gc(s) Gp(s)
IT CAN ALSO BE EXPRESSED IN THE FORM
Gc(s) = M(s)/E(s) = Kc.[1 + {1/(Ti.s)}.Td(s)] FOR IDEAL CASE
WHERE Kc = CONTROLLER GAIN, Ti = INTEGRAL ACTION TIME
AND Td = DERIVATIVE ACTION TIME.
PRACTICALLY, Gc(s) = [Kc(1+Ti.s).(1 + Td.s)]/[Ti(s)(1 + α.Td.s)]
αRANGES BETWEEN 1/6 TO 1/20. THE CONSTANT α ARISES
BECAUSE THE NORMAL ANALOG CONTROLLER IS
CONSTRUCTED BY ADDING A DERIVATIVE UNIT, BASED ON
THE USE OF LAG-LEAD NETWORK TO A PI CONTROLLER. THE
TRANSFER FN OF THE DERIVATIVE UNIT IS [Td.s + 1]/[α.Td.s + 1]

39. SYSTEM DESIGN
• A PROPORTIONAL TYPE FEEDBACK CONTROL SYSTEM IS ONE
WHICH DEVELOPS A CORRECTING EFFORT PROPORTIONAL TO THE
MAGNITUDE OF THE ACTUATING SIGNAL.
• THE LIMITATION OR DISADVANTAGE OF THIS SYSTEM IS THAT A
COMPROMISE IS NECESSARY IN SELECTING A FORWARD GAIN SO
THAT THE SIZE OF THE STEADY STATE ERROR AND THE MAXIMUM
OVERSHOOT OF THE OUTPUT RESPONSE ARE WITHIN THE
ACCEPTABLE TOLERANCES.
• BUT A COMPROMISE CAN NOT ALWAYS BE REACHED SINCE THE
SYSTEM CORRESPONDING TO THE GAIN SELECTED TO REALIZE A
MAXIMUM ACCEPTABLE STEADY STATE ERROR MAY HAVE EXCESS
OVERSHOOT IN ITS TIME RESPONSE OR MAY EVEN BE UNSTABLE.

40. SYSTEM DESIGN
• SO, TO MODIFY THE PERFORMANCE OF THE FEEDBACK
CONTROL SYSTEM, ONE ADOPTS EITHER
• DERIVATIVE CONTROL: TO IMPROVE THE OVERSHOOT BUT
NOT THE S S ERROR
• INTEGRAL CONTROL: BETTER S S ACCURACY BUT IS LESS
STABLE IN GENERAL.
• RATE FEEDBACK CONTROL

41. SYSTEM DESIGN
• THE DERIVATIVE CONTROL ESSENTIALLY IS AN ANTICIPATORY
TYPE OF CONTROL. IT MEASURES THE INSTANTANEOUS SLOPE OF
e(t), PREDICTS THE LARGE OVERSHOOT AHEAD OF TIME AND
MAKES PROPER CORRECTING EFFORT BEFORE THE OVERSHOOT
OCCURS.
• THE DERIVATIVE CONTROL EFFECTS THE SS ERROR OF THE
SYSTEM ONLY IF THE SS ERROR VARIES WITH TIME.
• SS ERROR OF A FEEDBACK SYSTEM IS THE DIFF BETWEEN THE SS
VALUES OF THE SYSTEM INPUT R(t) AND ITS OUTPUT C(t). THIS
ERROR IS VERY SMALL FOR A STABLE SYSTEM.
• SS ERROR OF A LINEAR CONTROL SYSTEM IS CONTROLLED BY THE
LOOP TR FN G(s).H(s) OF THE SYSTEM AND IT DEPENDS UPON THE
TYPE OF THE SYSTEM. SO, SS ERROR IS CONTROLLED BY THE
TYPE OF THE SYSTEM.

42. SYSTEM DESIGN
• THE HIGHER THE ORDER OF THE SYSTEM, THE MORE THE SYSTEM
TENDS TO BECOME UNSTABLE.
• PROPORTIONAL CONTROL X=Kc.E WHERE X=CONTROLLER
OUTPUT, Kc=GAIN = 1/PROP.BAND, E=ERROR SIGNAL
• INTEGRAL CONTROL X=[1/Ti.s].E WHERE s=LAPLACE OPERATOR d/dt,
Ti=INTEGRAL ACTION TIME
• PROP+INTEGRAL: X=Kc[(1/Ti.s) + 1].E
• PROP+DERIVATIVE X=Kc(1 + Td.s).E Td=DERIVATIVE ACTION TIME
• PID: X=Kc[(1/Ti.s) +Td.s + 1].E

43. SYSTEM DESIGN
• PROP. +DERIVATIVE CONTROL PROVIDES THE SMALLEST
MAXIMUM ERROR BECAUSE THE DERIVATIVE PART OF THE
RESPONSE ALLOWS THE PROPORTIONAL SENSITIVITY TO BE
INCREASED TO A HIGH VALUE.
• THE STABILIZATION TIME IS THE SMALLEST BECAUSE OF
THE DERIVATIVE ACTION. OFFSET IS ALLOWED BUT IS ONLY
HALF THAT EXPERIENCED WITHOUT DERIVATIVE ACTION.
• PID CONTROL HAS THE NEXT SMALLEST MAXIMUM
DEVIATION AND OFFSET IS ELIMINATED BECAUSE OF THE
INTEGRAL ACTION. STABILIZATION TIME IS INCREASED.

44. SYSTEM DESIGN
• PROPORTIONAL CONTROL HAS A LARGER MAXIMUM DEVIATION
THAN CONTROLLER WITH DERIVATIVE ACTION BECAUSE OF THE
ABSENCE OF THIS STABILIZING INFLUENCE. OFFSET IS ALSO
LARGER.
• PROP.+INTEGRAL CONTROL HAS NO OFFSET BECAUSE OF THE
INTEGRAL ACTION. THE UNSTABILIZING INFLUENCE OF INTEGRAL
RESPONSE IS REFLECTED IN THE LARGE MAXIMUM DEVIATION AND
THE PERSISTING DEVIATION.
• INTEGRAL CONTROL IS BEST SUITED FOR THE CONTROL OF
PROCESSES HAVING LITTLE OR NO ENERGY STORAGE AND THE
RESULTS OF THE COMPARISONS ARE NOT REPRESENTATIVE OF AN
INTEGRAL CONTROL. IN THIS PROCESS, THE RESULTS INDICATE A
LARGE MAXIMUM ERROR AND A LONG STABILIATION TIME.