Mosfet

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Mosfet

  1. 1. NT 2005 MOLECULAR AND NANOELECTRONICS MOSFET BY, A. POOJA SHUKLA 1821310006 M. Tech (I year)
  2. 2. INTRODUCTION TO TRANSISTOR  In 1947 by John Bardeen, Walter Brattain and William Shockley the transistor revolutionized the field of electronics  A transistor is a semiconductor device used to amplify and switch electronic signals and electrical power.  It is composed of semiconductor material with at least three terminals for connection to an external circuit.  The transistor is the fundamental building block of modern electronic devices.
  3. 3. TYPES OF TRANSISTOR  BJT  FET 1. MOSFET 2. JFET
  4. 4. FET TERMINALS SYMBOL
  5. 5. BJT AND FET BJT FET
  6. 6. WHAT IS MOSFET….???  The metal–oxide–semiconductor field-effect transistor (MOSFET, MOS-FET, or MOS FET) is a transistor used for amplifying or switching electronic signals.
  7. 7. MOSFET Gate Drain Source Metal Oxide Semiconductor Field Effect Transistor Source (Arsenic, Phosphorous, Boron) Drain (Arsenic, Phosphorous, Boron) Gate (Aluminum, Polysilicon)
  8. 8. MOSFET TERMINALS
  9. 9. TYPES OF MOSFET  n - MOS FET  p – MOS FET  CMOS FET
  10. 10. MOSFET TERMINALS SYMBOL D D G G S NMOS Enhancement S NMOS Depletion D G D G S PMOS Enhancement B S NMOS with Bulk Contact Channel
  11. 11. MOSFET STRUCTURE • This device is symmetric, so either of the n+ regions can be source or drain.
  12. 12. INTO TO FABRICATION…..!!! • Photolithography (photo) – Process of transferring pattern on mask to photoresist layer on wafer surface (pre-pattern the chip) • Etching – Process of permanently removed the unwanted part of design on wafer surface to get the desired pattern • Diffusion – Process of introducing dophant layer by movement of dophant atoms from high concentration to low concentration area at high temperature • Ion implantation – Process of introducing dophant layer by bombardment of high energy dophant ion in high electric field chamber • Oxidation – • Process of growing thick or thin SiO2 layer depend on oxide application CMP – Process to physically grind flat to have a planar surface for better exposure at photo process.
  13. 13. MOSFET Transistor Fabrication Steps
  14. 14. Building A MOSFET Transistor Using Silicon
  15. 15. It is done. Now, how does it work?
  16. 16. MOSFET OPERATION Step 1: Apply Gate Voltage SiO2 Insulator (Glass) Gate Source Drain 5 volts holes N N electrons P electrons to be transmitted Step 2: Excess electrons surface in channel, holes are repelled. Step 3: Channel becomes saturated with electrons. Electrons in source are able to flow across channel to Drain.
  17. 17. N-MOSFET – 4 electrical terminals • Source • Drain • Gate • Substrate – Connected to Gnd Gate Source Drain Substrate (Body) – Source and drain are only different in their interpretation • Terminal with lower voltage is the source (by convention) – Simplified symbol omits the substrate VG VS VD
  18. 18. N-MOSFET Gate Oxide Gate Source Polysilicon n+ Drain n+ p-substrate Bulk Contact CROSS-SECTION of NMOS Transistor P-type substrate N-type dopant for Source & Drain Inversion layer is formed to conduct electricity Field-Oxide (SiO2) p+ stopper
  19. 19. N-MOSFET • NMOS Behavior – When Gate (VG) is high (i.e. 1) the NMOS transistor acts as a closed switch • When VG = 0, the NMOS transistor is an open switch VG VS VG = "low" VD VG = "high"
  20. 20. P-MOSFET – Same 4 electrical terminals • Source • Drain • Gate • Substrate – Connected to VDD Gate Drain Substrate (Body) Source V DD – Again, source and drain are only different in their interpretation • Terminal with higher voltage is the source (by convention) – Simplified symbol omits the substrate VG VS VD
  21. 21. P-MOSFET Gate Oxide Gate Source Polysilicon p+ Drain p+ n-substrate Bulk Contact CROSS-SECTION of PMOS Transistor N-type substrate P-type dopant for Source & Drain Inversion layer is formed to conduct electricity Field-Oxide (SiO2) n+ stopper
  22. 22. P-MOSFET • PMOS Behavior – When Gate (VG) is low (i.e. 0) the PMOS transistor acts as a closed switch • When VG = 1, the PMOS transistor is an open switch VG VS VG = "high" VD VG = "low"
  23. 23. CMOSFET PROCESS FLOW WELL FORMATION ISOLATION FORMATION TRANSISTOR MAKING INTERCONNECTION PASSIVATION
  24. 24. CMOSFET A combination of both NMOS & PMOS technology Most basic example: inverter
  25. 25. CMOS FABRICATION PROCESS well formation • Start with clean p-type substrate (p-type wafer)
  26. 26. CMOS FABRICATION PROCESS well formation • Grow epitaxy layer (made from SiO2) as mask layer for well formation
  27. 27. CMOS FABRICATION PROCESS well formation Well will be formed here • By *photolithography and etching process, well opening are made *photolithography and etch processes are shown in next slides
  28. 28. CMOS FABRICATION PROCESS photoresist Si02 P-substrate • Photoresist coating (C) UV light • Masking and exposure under UV mask Opaque area P-substrate Transparent area light(E) • Resist dissolved after developed (D) – Pre-shape the well pattern at resist layer
  29. 29. ETCHING • Removing the unwanted P-substrate P-substrate pattern by wet etching • Resist clean • Desired pattern formed
  30. 30. CMOS FABRICATION PROCESS well formation Phosphorus ion • Ion bombardment by ion implantation • SiO2 as mask, uncovered area will exposed to dophant ion
  31. 31. CMOS FABRICATION PROCESS isolation formation Thick oxide • Increase SiO2 thickness by oxidation at high temperature • Oxide will electrically isolates nmos and pmos devices
  32. 32. CMOS FABRICATION PROCESS transistor making nmos will be formed here pmos will be formed here LOCOS (isolation structure) • By photolithography and etching process, pmos and nmos areas are defined
  33. 33. CMOS FABRICATION PROCESS transistor making Gate oxide • Grow very thin gate oxide at elevated temperature in very short time
  34. 34. CMOS FABRICATION PROCESS transistor making polysilicon • Deposit polysilicon layer
  35. 35. CMOS FABRICATION PROCESS transistor making gate • Photolithography (photo) and etching to form gate pattern
  36. 36. CMOS FABRICATION PROCESS transistor making Arsenic ion photoresist • Photo process to define the nmos’s active (source and drain) area and VDD contact • Ion implantation with Arsenic ion for n+ dophant. • Photoresist and polisilicon gate act as mask
  37. 37. CMOS FABRICATION PROCESS transistor making source drain VDD contact • Nmos’s Source and drain with VDD contact formation • Resist removal
  38. 38. CMOS FABRICATION PROCESS transistor making Boron ion photoresist • Photo process to define the GND contact and pmos’s active area (source and drain) • Ion implantation with boron ionto have p+ dophant • Photoresist and gate act as mask
  39. 39. CMOS FABRICATION PROCESS transistor making GND contact Pmos’s drain Pmos’ source • Pmos’s source and drain formation with GND contact • Resist removal
  40. 40. CMOS FABRICATION PROCESS interconnection SiO2 • Deposit SiO2 layer through out wafer surface
  41. 41. CMOS FABRICATION PROCESS interconnection contact • Photo and etching process to make contact
  42. 42. CMOS FABRICATION PROCESS interconnection Metal 1 • Metal 1 deposition throughout wafer surface
  43. 43. CMOS FABRICATION PROCESS interconnection • Photo and etching processes to pattern interconnection
  44. 44. Mask Layout
  45. 45. Mask Layout
  46. 46. Mask Layout
  47. 47. Mask Layout
  48. 48. A’ A Metal 1 oxide n+ n+ p+ N-well p-substrate p+
  49. 49. THANK YOU…….!!!

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